Ralph K. Cavin III - researchr alias

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Viewing Publication 1 - 52 from 52

2018

Nurturing the Growth of a National Infrastructure in Emerging TechnologiesRafic Z. Makki, Victor V. Zhirnov, Ralph K. Cavin III, Sami Issa, Marco Iansiti. pieee, 106(7):1126-1131, 2018. [doi]

2012

Science and Engineering Beyond Moore's LawRalph K. Cavin III, Paolo Lugli, Victor V. Zhirnov. pieee, 100(Centennial-Issue):1720-1749, 2012. [doi]

Prolog to the Section on Science and Engineering Beyond Moore's LawRalph K. Cavin III, Paolo Lugli, Victor V. Zhirnov. pieee, 100(Centennial-Issue):1718-1719, 2012. [doi]

2010

Device and Architecture Outlook for Beyond CMOS SwitchesKerry Bernstein, Ralph K. Cavin III, Wolfgang Porod, Alan C. Seabaugh, Jeff Welser. pieee, 98(12):2169-2184, 2010. [doi]

Nanoelectronics Research for Beyond CMOS Information ProcessingGeorge Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida. pieee, 98(12):1986-1992, 2010. [doi]

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and GapsMichel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida. pieee, 98(12):1993-2004, 2010. [doi]

Memory Devices: Energy-Space-Time TradeoffsVictor V. Zhirnov, Ralph K. Cavin III, Stephan Menzel, Eike Linn, Sebastian Schmelzer, Dennis Bräuhaus, Christina Schindler, Rainer Waser. pieee, 98(12):2185-2200, 2010. [doi]

2009

Scaling beyond CMOS: Turing-Heisenberg RapproachmentVictor V. Zhirnov, Ralph K. Cavin III. esscirc 2009: 16-22 [doi]

2008

Boolean Logic and Alternative Information-Processing DevicesGeorge Bourianoff, Joe E. Brewer, Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov. Computer, 41(5):38-46, 2008. [doi]

Emerging Nanoscale Memory and Logic Devices: A Critical AssessmentJames A. Hutchby, Ralph K. Cavin III, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff. Computer, 41(5):28-32, 2008. [doi]

Emerging Research ArchitecturesRalph K. Cavin III, James A. Hutchby, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff. Computer, 41(5):33-37, 2008. [doi]

The Viability of Cellular Automata Architectures for General Purpose ComputingVictor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III. ersa 2008: 321-333

An Assessment of Integrated Digital Cellular Automata ArchitecturesVictor V. Zhirnov, Ralph K. Cavin III, Greg Leeming, Kosmas Galatsis. Computer, 41(1):38-44, 2008. [doi]

2006

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signalingRizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards. jssc, 41(2):461-473, 2006. [doi]

2005

Future devices for information processingRalph K. Cavin III, Victor V. Zhirnov. esscirc 2005: 7-12 [doi]

2004

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capabilityRizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards. tvlsi, 12(8):876-880, 2004. [doi]

2003

2002

Delay and power model for current-mode signaling in deep submicron global interconnectsRizwan Bashirullah, Wentai Liu, Ralph K. Cavin III. cicc 2002: 513-516 [doi]

2000

Integrated parametric timing optimization of digital systemsHong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III. tcad, 19(4):482-489, 2000. [doi]

1997

Clocking Optimization and Distribution in Digital Systems with Scheduled SkewsHong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III. vlsisp, 16(2-3):131-147, 1997. [doi]

A CMOS high-speed data recovery circuit using the matched delay sampling techniqueJin-Ku Kang, Wentai Liu, Ralph K. Cavin III. jssc, 32(10):1588-1596, 1997. [doi]

The delay vernier pattern generation techniqueGary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III. jssc, 32(4):551-562, 1997. [doi]

1995

1994

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolutionC. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III. jssc, 29(3):340-349, March 1994. [doi]

Timing constraints for wave-pipelined systemsC. Thomas Gray, Wentai Liu, Ralph K. Cavin III. tcad, 13(8):987-1004, 1994. [doi]

Circuit delay calculation considering data dependent delaysC. Thomas Gray, Wentai Liu, Ralph K. Cavin III, Hong-Yean Hsieh. integration, 17(1):1-23, 1994. [doi]

A 250-MHz wave pipelined adder in 2-/spl mu/m CMOSWentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III. jssc, 29(9):1117-1128, September 1994. [doi]

1993

A bit-serial VLSI architecture for generating moments in real-timeWentai Liu, Su-Shing Chen, Ralph K. Cavin III. tsmc, 23(2):539-546, 1993. [doi]

1991

Theoretical and Practical Issues in CMOS Wave PipeliningC. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III. vlsi 1992: 397-409

1990

1989

The Semiconductor Research Corporation: Cooperative researchRalph K. Cavin III, Larry W. Sumney, Robert M. Burger. pieee, 77(9):1327-1344, 1989. [doi]

Hamiltonian Cycles in the Shuffle-Exchange NetworkWentai Liu, Thomas H. Hildebrandt, Ralph K. Cavin III. TC, 38(5):745-750, 1989.

1988

Bit-level concurrency in real-time geometric feature extractionsWentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III. cvpr 1988: 957-962 [doi]

Exploiting Bit Level Concurrency in Real-Time Geometric Feature ExtractionsWentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III. isca 1988: 167-174

Rasterization theory, architectures, and implementations for a class of two-dimensional problemsWentai Liu, Ralph K. Cavin III. integration, 6(2):179-199, 1988. [doi]

1986

A perspective on CMOS technology trendsWilliam C. Holton, Ralph K. Cavin III. pieee, 74(12):1646-1668, 1986. [doi]

1984

The Impact of ICs on Computer TechnologyRobert M. Burger, Ralph K. Cavin III, William C. Holton, Larry W. Sumney. Computer, 17(10):88-95, 1984.

Introduction to the SRC design sciences programRalph K. Cavin III. dac 1984: 216-217 [doi]

1983

Microelectronic architectures and devices for signal and symbol processingRalph K. Cavin III, Noel R. Strader. integration, 1(4):283-304, 1983. [doi]

1982

Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processesStephen K. Jones, Ralph K. Cavin III, William M. Reed. TIT, 28(2):318-329, 1982.

1980

An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy ProbabilitiesStephen K. Jones, Ralph K. Cavin III, Donald A. Johnston. tcom, 28(12):2019-2020, 1980. [doi]

1977

Distributed parameter system optimum control design via finite element discretizationRalph K. Cavin III, S. C. Tandon. automatica, 13(6):611-614, 1977. [doi]

Dynamic Modeling and Control of Digital Communication NetworksStephen K. Jones, Ralph K. Cavin III. Computer, 10(11):60-64, 1977. [doi]

On the Maximum Average Throughput Rate for a Tandem Node NetworkStephen K. Jones, Ralph K. Cavin III, J. N. Holyoak. tcom, 25(10):1240-1242, 1977. [doi]

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