Table of Contents

• Calculus of space-optimal mappings of systolic algorithms on processor arraysPhilippe Clauss, Catherine Mongenet, Guy-René Perrin. 4-18 [doi]
• A processor-time minimal systolic array for transitive closureChris J. Scheiman, Peter R. Cappello. 19-30 [doi]
• Systolic array implementation of nested loop programsJichun Bu, Ed F. Deprettere, Lothar Thiele. 31-42 [doi]
• The bit-serial systolic back-projection engine (BSSBPE)Richard H. Bayford. 43-54 [doi]
• A database machine based on surrogate filesSoon Myoung Chung. 55-66 [doi]
• Systolic architectures for decoding Reed-Solomon codesJohn Nelson, Abdur Rahman, Eamonn McQuade. 67-77 [doi]
• Mapping high-dimension wavefront computations to siliconChen-Mie Wu, Robert Michael Owens, Mary Jane Irwin. 78-89 [doi]
• Systolic architecture for 2-D rank order filteringJenq-Neng Hwang, Jing-Ming Jong. 90-99 [doi]
• Scheduling affine parameterized recurrences by means of Variable Dependent Timing FunctionsChristophe Mauras, Patrice Quinton, Sanjay V. Rajopadhye, Yannick Saouter. 100-110 [doi]
• The Logic Description GeneratorMaya B. Gokhale, Andrew Kopser, Sara P. Lucas, Ronald G. Minnich. 111-120 [doi]
• Recursive algorithms for AR spectral estimation and their array realizationsChi-Min Liu, Chein-Wei Jen. 121-132 [doi]
• Analysing parametrised designs by non-standard interpretationWayne Luk. 133-144 [doi]
• Systolic VLSI compiler (SVC) for high performance vector quantisation chipsY. Hu, John V. McCanny, M. Yan. 145-155 [doi]
• Extensions to linear mapping for regular arrays with complex processing elementsJan Rossee, Francky Catthoor, Hugo De Man. 156-167 [doi]
• Design of run-time fault-tolerant arrays of self-checking processing elementsJens Franzen. 168-179 [doi]
• GRAPE: a special-purpose computer for N-body problemsJunichiro Makino, Tomoyoshi Ito, Toshikazu Ebisuzaki, Daiichiro Sugimoto. 180-189 [doi]
• Building blocks for a new generation of application specific computing systemsBrent Baxter, George W. Cox, Thomas R. Gross, H. T. Kung, David R. O'Hallaron, Craig Peterson, Jon A. Webb, Paul Wiley. 190-201 [doi]
• Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessorDhabaleswar Kumar Panda, Kai Hwang. 202-213 [doi]
• Massively parallel architecture: application to neural net emulation and image reconstructionDidier Lattard, Bernard Faure, Guy Mazaré. 214-225 [doi]
• A real-time software programmable processor for HDTV and stereo scope signalsTakao Nishitani, Ichiro Tamitani, Hidenobu Harasaki, Mitsuharu Yano. 226-234 [doi]
• Mapping algorithms onto the TUT cellular array processorJouko O. Viitanen, Tapio Korpiharju, Jarmo Takala, Hannu Kiminkinen. 235-246 [doi]
• A 3-D wafer scale architecture for early vision processingScott T. Toborg. 247-258 [doi]
• Algorithmic mapping of neural network models onto parallel SIMD machinesV. K. Prasanna Kumar, K. Wojtek Przytula. 259-271 [doi]
• Implementation of systolic algorithms using pipelined functional unitsMiguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero. 272-283 [doi]
• Array processing on finite polynomial ringsNeil M. Wigley, Graham A. Jullien. 284-295 [doi]
• The RAP: a ring array processor for layered network calculationsNelson Morgan, James Beck, Phil Kohn, Jeffrey A. Bilmes, Eric Allman, Joachim Beer. 296-308 [doi]
• Linear arrays for residue mappersZarir B. Sarkari, Alexander Skavantzos. 309-316 [doi]
• A fault-tolerant two-dimensional sorting networkJosef G. Krammer, Hendrikus Arif. 317-328 [doi]
• Channel complexity analysis for reconfigurable VLSI/WSI processor arraysPhill K. Rhee, Jung H. Kim. 329-340 [doi]
• Digit-serial DSP architecturesKeshab K. Parhi, Ching-Yi Wang. 341-351 [doi]
• PASIC. A sensor/processor array for computer visionKeping Chen, Per-Erik Danielsson, Anders Åström. 352-366 [doi]
• An analog VLSI array processor for classical and connectionist AIJonathan Wayne Mills, Charles A. Daffinger. 367-378 [doi]
• Systolic two-port adaptor for high performance wave digital filteringRajinder Jit Singh, John V. McCanny. 379-388 [doi]
• An improved multilayer neural model and array processor implementationC. C. Chiang, H.-C. Fu. 389-400 [doi]
• Reconfiguration of FFT arrays: a flow-driven approachAnna Antola, Nello Scarabottolo. 401-413 [doi]
• Towards the automated design of application specific array processors (ASAPs)A. P. Marriott, Andrew W. G. Duller, Richard H. Storer, Andrew R. Thomson, Mike R. Pout. 414-425 [doi]
• Fault-tolerant array processors using N-and-half-track switchesJack S. N. Jean. 426-437 [doi]
• Domain flow and streaming architecturesE. Theodore L. Omtzigt. 438-447 [doi]
• An improved systolic extended Euclidean algorithm for Reed-Solomon decoding: design and implementationRory Doyle, Patrick Fitzpatrick, John Nelson. 448-456 [doi]
• Digit-serial VLSI microarchitectureStewart G. Smith, Julian G. Payne, Ralph W. Morgan. 457-468 [doi]
• CMOS VLSI Lukasiewicz logic arraysJonathan Wayne Mills, Charles A. Daffinger. 469-480 [doi]
• Dynamic systolic associative memory chipG. J. Lipovski. 481-492 [doi]
• ASP modules: building-blocks for application-specific massively parallel processorsR. M. Lea. 493-504 [doi]
• Designing specific systolic arrays with the API15C chipPatrice Frison, Eric Gautrin, Dominique Lavenier, J.-L. Scharbarg. 505-517 [doi]
• A prototype for a fault tolerant parallel digital signal processorBruce R. Musicus, Amnon Aliphas, Alexander J. Wei. 518-529 [doi]
• Byte-serial convolversLuigi Dadda. 530-541 [doi]
• A VLSI architecture for simplified arithmetic Fourier transform algorithmIrving S. Reed, Ming-Tang Shih, E. Hendon, Trieu-Kien Truong, Donald W. Tufts. 542-553 [doi]
• Fine-grain system architectures for systolic emulation of neural algorithmsUlrich Ramacher, Wolfgang Raab. 554-566 [doi]
• Programming environment for a line processor-SYMPATI-2Pascal Fernandez, Pascal Adam, Didier Juvin, Jean-Luc Basille. 567-578 [doi]
• A feedback concentrator for the Image Understanding ArchitectureDeepak Rana, Charles C. Weems. 579-590 [doi]
• A design methodology for fixed-size systolic arraysJichun Bu, Ed F. Deprettere, Patrick M. Dewilde. 591-602 [doi]
• A formal design methodology for parallel architecturesKhaled M. Elleithy, Magdy A. Bayoumi. 603-614 [doi]
• A multiple-level heterogeneous architecture for image understandingDavid B. Shu, J. Gregory Nash, Charles C. Weems. 615-627 [doi]
• Application specific VLSI architectures based on De Bruijn graphsDhiraj K. Pradhan. 628-640 [doi]
• A graph-based approach to map matrix algorithms onto local-access processor arraysJaime H. Moreno, Tomás Lang. 641-652 [doi]
• Application-specific coprocessor computer architectureYaohan Chu. 653-664 [doi]
• Embedding pyramids in array processors with pipelined bussesZicheng Guo, Rami G. Melhem. 665-676 [doi]
• Implementation of ANN on RISC processor arrayAtsunobu Hiraiwa, Masahiro Fujita, Shigeru Kurosu, Shigeru Arisawa, Makoto Inoue. 677-688 [doi]
• Systolic-based computing machinery for radar signal processing studiesSimon Haykin, Peter Weber, Bob Cho, Terry Greenlay, Jim Orlando, Cong Deng, Richard Mann. 689-699 [doi]
• A systolic array for nonlinear adaptive filtering and pattern recognitionJ. G. McWhirter, David S. Broomhead, T. J. Shepherd. 700-711 [doi]
• Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealingC. S. Jeong, M. H. Kim. 712-721 [doi]
• The design of a high-performance scalable architecture for image processing applicationsC. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III. 722-733 [doi]
• Testing a motion estimator arrayWilliam P. Marnane, Will R. Moore. 734-745 [doi]
• Spacetime-minimal systolic architectures for Gaussian elimination and the algebraic path problemAbdelhamid Benaini, Yves Robert. 746-757 [doi]
• Two-level pipelined implementation of systolic block Householder transformation with application to RLS algorithmK. J. Ray Liu, Shih Fu Hsieh, Kung Yao. 758-769 [doi]
• Bit-level systolic algorithm for the symmetric eigenvalue problemJean-Marc Delosme. 770-781 [doi]
• A practical runtime test method for parallel lattice-gas automataRichard K. Squier, Kenneth Steiglitz. 782-793 [doi]
• A systolic array programming languageP. S. Tseng. 794-803 [doi]