Will R. Moore - researchr alias

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Viewing Publication 1 - 12 from 12

2007

Extending gate-level diagnosis tools to CMOS intra-gate faultsXinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud. iet-cdt, 1(6):685-693, 2007. [doi]

2005

Stuck-open fault diagnosis with stuck-at modelXinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud. ets 2005: 182-187 [doi]

A novel stuck-at based method for transistor stuck-open fault diagnosisXinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud. itc 2005: 9 [doi]

1998

Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing ParadigmOvidio V. Maiuri, Will R. Moore. vts 1998: 22-27 [doi]

1990

Silicon models of associative learning in ::::Aplysia::::Howard C. Card, Will R. Moore. NN, 3(3):333-346, 1990. [doi]

Testing a motion estimator arrayWilliam P. Marnane, Will R. Moore. asap 1990: 734-745 [doi]

1989

Vlsi Devices and Circuits for Neural NetworksHoward C. Card, Will R. Moore. IJNS, 1(2):149-165, 1989. [doi]

A semantic network architecture for artificial intelligence processingJosé G. Delgado-Frias, Will R. Moore. ictai 1989: 162-167 [doi]

Imperfectly connected 2D arrays for image processingJohn A. Trotter, Will R. Moore. ftcs 1989: 88-92 [doi]

1988

Parallel architectures for AI semantic network processingJosé G. Delgado-Frias, Will R. Moore. kbs, 1(5):259-265, 1988. [doi]

Testing of VLSI regular arraysWilliam P. Marnane, Will R. Moore. iccd 1988: 145-148 [doi]

1986

A review of fault-tolerant techniques for the enhancement of integrated circuit yieldWill R. Moore. pieee, 74(5):684-698, 1986. [doi]

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