Abstract is missing.
- The fault tolerance approach of the Advanced Architecture Onboard ProcessorMichael J. Iacoponi, David K. Vail. 6-12 [doi]
- Dependable onboard computer systems with a new method-stepwise negotiating votingNobuyasu Kanekawa, Hideo Maejima, Hatsuhiko Kato, Hirokazu Ihara. 13-19 [doi]
- Use of a functional programming model in fault tolerant parallel processingRichard E. Harper, Gail Nagle, Martin A. Serrano. 20-26 [doi]
- An economical scan design for sequential logic test generationKwang-Ting Cheng, Vishwani D. Agrawal. 28-35 [doi]
- Row/column pattern sensitive fault detection in RAMs via built-in self-testManoj Franklin, Kewal K. Saluja, Kozo Kinoshita. 36-43 [doi]
- Advanced automatic test pattern generation techniques for path delay faultsMichael H. Schulz, Karl Fuchs, Franz Fink. 44-51 [doi]
- On self-diagnosable multiprocessor systems: diagnosis by the comparison approachAbhijit Sengupta, Anton T. Dahbura. 54-61 [doi]
- Fault diagnosis for sparsely interconnected multiprocessor systemsDouglas M. Blough, Gregory F. Sullivan, Gerald M. Masson. 62-69 [doi]
- Distributed syndrome decoding for regular interconnected structuresArun K. Somani, Vinod K. Agarwal. 70-77 [doi]
- Fault-tolerance in a high-speed 2D convolver/correlator: StarlocLeonard M. Napolitano Jr., David D. Andaleon, K. R. Berry, P. R. Bryson, S. R. Klapp, J. E. Leeper, G. Robert Redinbo. 80-87 [doi]
- Imperfectly connected 2D arrays for image processingJohn A. Trotter, Will R. Moore. 88-92 [doi]
- Comprehensive evaluation of a two-dimensional configurable arrayOnat Menzilcioglu, H. T. Kung, Siang Wun Song. 93-100 [doi]
- Easily testable PLA-based finite state machinesSrinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton. 102-109 [doi]
- The design of random-testable sequential circuitsHans-Joachim Wunderlich. 110-117 [doi]
- BALLAST: a methodology for partial scan designRajesh Gupta, Melvin A. Breuer. 118-125 [doi]
- Design of fault-tolerant clocks with realistic failure assumptionsNagesh Vasanthavada, Philip Thambidurai, Peter N. Marinos. 128-133 [doi]
- A fast timing verification method based on the independence of unitsTomohiro Yoneda, Kazutoshi Nakade, Yoshihiro Tohma. 134-141 [doi]
- Clock synchronization in MAFTPhilip M. Thambidurai, Alan M. Finn, Roger M. Kieckhafer, Chris J. Walter. 142-149 [doi]
- Ultrahigh reliability estimates for systems exhibiting globally time-dependent failure processesRobert Geist, Mark Smotherman, Michael Brown. 152-158 [doi]
- Evaluation of fault-tolerant systems with nonhomogeneous workloadsB. E. Aupperle, John F. Meyer, Lu Wei. 159-166 [doi]
- Modeling of fault-tolerant techniques in hierarchical systemsYuan-Bao Shieh, Dipak Ghosal, Satish K. Tripathi. 167-174 [doi]
- Performability of a token bus network under transient fault conditionsJohn F. Meyer, K. H. Muralidhar, William H. Sanders. 175-182 [doi]
- Using passive replicates in Delta-4 to provide dependable distributed computingNeil A. Speirs, Peter A. Barrett. 184-190 [doi]
- Distance agreement protocolsKlaus Echtle. 191-198 [doi]
- A design for a fault-tolerant, distributed implementation of LindaAndrew Xu, Barbara Liskov. 199-206 [doi]
- Some new EC/AUED codesJehoshua Bruck, Mario Blaum. 208-215 [doi]
- Unidirectional 9-bit byte error detecting codes for computer memory systemsLarry A. Dunning, Gur Dial, Murali R. Varanasi. 216-221 [doi]
- Byte unidirectional error correcting codesBella Bose. 222-228 [doi]
- Design of efficient balanced codesSulaiman Al-Bassam, Bella Bose. 229-236 [doi]
- Defects and reliability analysis of large software systems: field experienceYtzhak H. Levendel. 238-244 [doi]
- Fault tolerant multiprocessor for digital switching systemsTakahiko Yamada, Satoshi Ogawa. 245-252 [doi]
- F-T in telecommunications networks: state, perspectives, trendsMichele Morganti. 253-258 [doi]
- Reliable design of high-speed cache and control store memoriesRobert W. Horst. 259-266 [doi]
- A system for supporting multi-language versions for software fault toleranceJames M. Purtilo, Pankaj Jalote. 268-274 [doi]
- Fault identification in robust data structuresA. Ravichandran, Krishna Kant. 275-282 [doi]
- Formal verification of programs with exceptionsJean-Chrysostome Bolot, Pankaj Jalote. 283-290 [doi]
- Pseudo-exhaustive test and segmentation: formal definitions and extended fault coverage resultsJon G. Jr. Udell, Edward J. McCluskey. 292-298 [doi]
- Computations over finite monoids and their test complexityBernd Becker, Uwe Sparmann. 299-306 [doi]
- A new approach of test confidence estimationMireille Jacomino, Rene David. 307-314 [doi]
- Estimation of maximum currents for fault tolerant design of power distribution systems in integrated circuitsShamsul Chowdhury. 316-322 [doi]
- A proposal for a fault-tolerant binary hypercube architectureSiu-Cheung Chau, Arthur L. Liestman. 323-330 [doi]
- Message routing in HARTS with faulty componentsAlan Olson, Kang G. Shin. 331-338 [doi]
- Evaluation of error detection schemes using fault injection by heavy-ion radiationUlf Gunneflo, Johan Karlsson, Jan Torin. 340-347 [doi]
- Fault injection for dependability validation of fault-tolerant computing systemsJean Arlat, Yves Crouzet, Jean-Claude Laprie. 348-355 [doi]
- Understanding large system failures-a fault injection experimentRam Chillarege, Nicholas S. Bowen. 356-363 [doi]
- Workload redistribution for fault-tolerance in a hard real-time distributed computing systemShri Balaji, Lawrence Jenkins, Lalit M. Patnaik, Prem Shankar Goel. 366-373 [doi]
- Modelling correlated transient failures in fault-tolerant systemsC. Mani Krishna, Adit D. Singh. 374-381 [doi]
- Optimal control of latent fault accumulationM. J. Iacoponi. 382-388 [doi]
- A strongly fault-secure and strongly code-disjoint realization of combinational circuitsTakashi Nanya, Masatoshi Uchida. 390-397 [doi]
- A generalized theory of fail-safe systemsMichael Nicolaidis, S. Noraz, Bernard Courtois. 398-406 [doi]
- Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkersNiraj K. Jha. 407-414 [doi]
- Control-flow checking using watchdog assists and extended-precision checksumsNirmal R. Saxena, Edward J. McCluskey. 428-435 [doi]
- A study of time-redundant fault tolerance techniques for high-performance pipelined computersGurindar S. Sohi, Manoj Franklin, Kewal K. Saluja. 436-443 [doi]
- A theoretical investigation of generalized voters for redundant systemsPaul R. Lorczak, Alper K. Caglayan, Dave E. Eckhardt. 444-451 [doi]
- Replication within atomic actions and conversations: a case study in fault-tolerance dualityLuigi Vincenzo Mancini, Santosh K. Shrivastava. 454-461 [doi]
- art: support for real-time atomic transactionsAhmed Gheith, Karsten Schwan. 462-469 [doi]
- Language constructs for timed atomic commitmentSusan B. Davidson, Insup Lee, Victor Fay Wolfe. 470-477 [doi]
- Neural computing for built-in self-repair of embedded memory arraysPinaki Mazumder, Jih-Shyr Yih. 480-487 [doi]
- Bi-level reconfigurations of fault tolerant arrays in bi-modal computational environmentsRami G. Melhem. 488-495 [doi]
- An automorphic approach to the design of fault-tolerant multiprocessorsShantanu Dutt, John P. Hayes. 496-503 [doi]
- On the provision of backward error recovery in production programming languagesSamuel T. Gregory, John C. Knight. 506-511 [doi]
- Hardware assisted recovery from transient errors in redundant processing systemsStuart J. Adams. 512-519 [doi]
- Recoverable distributed shared virtual memory: memory coherence and storage structuresKun-Lung Wu, W. Kent Fuchs. 520-527 [doi]
- An analytical model for computing hypercube availabilityChita R. Das, Jong Kim. 530-537 [doi]
- Fail-softness evaluation in multiple-bus local computer networksVikram V. Karmarkar, Jon G. Kuhl. 538-544 [doi]
- Detailed modeling of fault-tolerant processor arraysNoé Lopez-Benitez, José A. B. Fortes. 545-552 [doi]
- Characterization and design of sequentially t-diagnosable systemsShi-ze Huang, Jie Xu, Tinghuai Chen. 554-559 [doi]
- Probabilistic diagnosis of multiprocessor systems with arbitrary connectivityDonald S. Fussell, Sampath Rangarajan. 560-565 [doi]
- Reliability analysis and comparison of two fail-op/fail-op/fail-safe architecturesArun K. Somani, Tushar R. Sarnaik. 566-573 [doi]