Edward J. McCluskey - researchr alias

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Viewing Publication 1 - 100 from 214

2016

State of the JournalPaolo Montuschi, Edward J. McCluskey, Samarjit Chakraborty, Jason Cong, Ramón M. Rodríguez-Dagnino, Fred Douglis, Lieven Eeckhout, Gernot Heiser, Sushil Jajodia, Ruby B. Lee, Dinesh Manocha, Tomás F. Pena, Isabelle Puaut, Hanan Samet, Donatella Sciuto. TC, 65(7):2014-2018, 2016. [doi]

2010

Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test PatternsAhmad A. Al-Yamani, Edward J. McCluskey. et, 26(5):513-521, 2010. [doi]

2008

2007

Test Set Reordering Using the Gate Exhaustive Test MetricKyoung Youn Cho, Edward J. McCluskey. vts 2007: 199-204 [doi]

California scan architecture for high quality and low power testingKyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey. itc 2007: 1-10 [doi]

2006

Session AbstractErik Chmelar, Edward J. McCluskey. vts 2006: 156-157 [doi]

Classifying Bad Chips and Ordering Test SetsFrançois-Fabien Ferhani, Edward J. McCluskey. itc 2006: 1-10 [doi]

2005

2004

Test quality for high level structural testAhmad A. Al-Yamani, Edward J. McCluskey. hldvt 2004: 109-114 [doi]

Speed Clustering of Integrated CircuitsKenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra. itc 2003: 1128-1137 [doi]

ELF-Murphy Data on Defects and Test SetsEdward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra. vts 2004: 16-22 [doi]

Delay Defect Screening using Process Monitor StructuresSubhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger. vts 2004: 43-52 [doi]

Reconfigurable Architecture for Autonomous Self-RepairSubhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey. dt, 21(3):228-240, 2004. [doi]

Efficient Design Diversity Estimation for Combinational CircuitsSubhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey. TC, 53(11):1483-1492, 2004. [doi]

A Multi-Configuration Strategy for an Application Dependent Testing of FPGAsMehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure. vts 2004: 154-170 [doi]

2003

Built-In Reseeding for Serial BistAhmad A. Al-Yamani, Edward J. McCluskey. vts 2003: 63-68 [doi]

Seed encoding with LFSRs and cellular automataAhmad A. Al-Yamani, Edward J. McCluskey. dac 2003: 560-565 [doi]

Bist Reseeding with very few SeedsAhmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey. vts 2003: 69-76 [doi]

2002

Testing Digital Circuits with ConstraintsAhmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey. dft 2002: 195-206 [doi]

Diagnosis of Sequence-Dependent ChipsChien-Mo James Li, Edward J. McCluskey. vts 2002: 187-192 [doi]

Debating the Future of Burn-InEdward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers. vts 2002: 311-314 [doi]

Dependable Reconfigurable Computing Design Diversity and Self RepairSubhasish Mitra, Edward J. McCluskey. eh 2002: 5 [doi]

Design for Testability and Testing of IEEE 1149.1 Tap ControllerSubhasish Mitra, Edward J. McCluskey, Samy Makar. vts 2002: 247-252 [doi]

A Design Diversity Metric and Analysis of Redundant SystemsSubhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey. TC, 51(5):498-510, 2002. [doi]

Control-flow checking by software signaturesNahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey. tr, 51(1):111-122, 2002. [doi]

Error detection by duplicated instructions in super-scalar processorsNahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey. tr, 51(1):63-75, 2002. [doi]

Error detection by selective procedure call duplication for low energy consumptionNahmsuk Oh, Edward J. McCluskey. tr, 51(4):392-402, 2002. [doi]

ED4I: Error Detection by Diverse Data and Duplicated InstructionsNahmsuk Oh, Subhasish Mitra, Edward J. McCluskey. TC, 51(2):180-199, 2002. [doi]

Fault Grading FPGA Interconnect Test ConfigurationsMehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey. itc 2002: 608-617 [doi]

Experimental Results for Slow-Speed TestingChao-Wen Tseng, James Li, Edward J. McCluskey. vts 2002: 37-42 [doi]

2001

Performance Evaluation of Checksum-Based ABFTAhmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey. dft 2001: 461 [doi]

A memory coherence technique for online transient error recovery of FPGA configurationsWei-Je Huang, Edward J. McCluskey. fpga 2001: 183-192 [doi]

Column-Based Precompiled Configuration Techniques for FPGAWei-Je Huang, Edward J. McCluskey. fccm 2001: 137-146 [doi]

Fast Run-Time Fault Location in Dependable FPGA-Based ApplicationsWei-Je Huang, Subhasish Mitra, Edward J. McCluskey. dft 2001: 206-214 [doi]

Diagnosis of Tunneling OpensChien-Mo James Li, Edward J. McCluskey. vts 2001: 22-27 [doi]

Diversity Techniques for Concurrent Error DetectionSubhasish Mitra, Edward J. McCluskey. isqed 2001: 249-250 [doi]

Design of Redundant Systems Protected Against Common-Mode FailuresSubhasish Mitra, Edward J. McCluskey. vts 2001: 190-197 [doi]

Techniques for Estimation of Design Diversity for Combinational Logic CircuitsSubhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey. dsn 2001: 25-36 [doi]

Design Diversity for Concurrent Error Detection in Sequential Logic CircutsSubhasish Mitra, Edward J. McCluskey. vts 2001: 178-183 [doi]

Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection LatencyNahmsuk Oh, Edward J. McCluskey. dft 2001: 182 [doi]

Bit-fixing in pseudorandom sequences for scan BISTNur A. Touba, Edward J. McCluskey. tcad, 20(4):545-555, 2001. [doi]

Testing for resistive opens and stuck opensChao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey. itc 2001: 1049-1058

Multiple-output propagation transition fault testChao-Wen Tseng, Edward J. McCluskey. itc 2001: 358-366

MINVDD Testing for Weak CMOS ICsChao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh. vts 2001: 339-345 [doi]

An Evaluation of Pseudo Random Testing for Detecting Real DefectsChao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson. vts 2001: 404-410 [doi]

On-line testing and recovery in TMR systems for real-time applicationsShu-Yi Yu, Edward J. McCluskey. itc 2001: 240-249

Permanent Fault Repair for FPGAs with Limited Redundant AreaShu-Yi Yu, Edward J. McCluskey. dft 2001: 125-133 [doi]

2000

Transient errors and rollback recovery in LZ compressionWei-Je Huang, Edward J. McCluskey. prdc 2000: 128-138 [doi]

A Reliable LZ Data Compressor on Reconfigurable CoprocessorsWei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey. fccm 2000: 249-258 [doi]

Testing for tunneling opensChien-Mo James Li, Edward J. McCluskey. itc 2000: 85-94

Stuck-fault tests vs. actual defectsEdward J. McCluskey, Chao-Wen Tseng. itc 2000: 336-343

Which concurrent error detection scheme to choose ?Subhasish Mitra, Edward J. McCluskey. itc 2000: 985-994

Word Voter: A New Voter Design for Triple Modular Redundant SystemsSubhasish Mitra, Edward J. McCluskey. vts 2000: 465-470 [doi]

Fault Escapes in Duplex SystemsSubhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey. vts 2000: 453-458 [doi]

Combinational logic synthesis for diversity in duplex systemsSubhasish Mitra, Edward J. McCluskey. itc 2000: 179-188

Efficient Multiplexer Synthesis TechniquesSubhasish Mitra, LaNae J. Avra, Edward J. McCluskey. dt, 17(4):90-97, 2000. [doi]

Common-mode failures in redundant VLSI systems: a surveySubhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey. tr, 49(3):285-295, 2000. [doi]

Dependable Computing and Online Testing in Adaptive and Configurable SystemsNirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey. dt, 17(1):29-41, 2000. [doi]

Software-implemented EDAC protection against SEUsPhilip P. Shirvani, Nirmal R. Saxena, Edward J. McCluskey. tr, 49(3):273-284, 2000. [doi]

Cold Delay Defect ScreeningChao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu. vts 2000: 183-188 [doi]

An ACS Robotic Control Algorithm with Fault Tolerant CapabilitiesShu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey. fccm 2000: 175-184 [doi]

1999

1998

1997

SHOrt voltage elevation (SHOVE) test for weak CMOS ICsJonathan T.-Y. Chang, Edward J. McCluskey. vts 1997: 446 [doi]

ATPG for scan chain latches and flip-flopsSamy Makar, Edward J. McCluskey. vts 1997: 364-369 [doi]

An output encoding problem and a solution techniqueSubhasish Mitra, LaNae J. Avra, Edward J. McCluskey. iccad 1997: 304-307 [doi]

Scan Synthesis for One-Hot SignalsSubhasish Mitra, LaNae J. Avra, Edward J. McCluskey. itc 1997: 714-722

High-Level Synthesis for Orthogonal ScaRobert B. Norwood, Edward J. McCluskey. vts 1997: 370-375 [doi]

Parallel Signatur Analysis Design with Bounds on AliasingNirmal R. Saxena, Edward J. McCluskey. TC, 46(4):425-438, 1997.

Pseudo-Random Pattern Testing of Bridging FaultsNur A. Touba, Edward J. McCluskey. iccd 1997: 54-60

Logic synthesis of multilevel circuits with concurrent error detectionNur A. Touba, Edward J. McCluskey. tcad, 16(7):783-789, 1997. [doi]

1996

Quantitative analysis of very-low-voltage testingJonathan T.-Y. Chang, Edward J. McCluskey. vts 1996: 332-337 [doi]

Detecting Delay Flaws by Very-Low-Voltage TestingJonathan T.-Y. Chang, Edward J. McCluskey. itc 1996: 367-376

Analysis and Detection of Timing Failures in an Experimental Test ChipPiero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell. itc 1996: 691-700

Synthesis-for-scan and scan chain orderingRobert B. Norwood, Edward J. McCluskey. vts 1996: 87-92 [doi]

Orthogonal Scan: Low-Overhead Scan for Data PathsRobert B. Norwood, Edward J. McCluskey. itc 1996: 659-668

Counting Two-State Transition-Tour SequencesNirmal R. Saxena, Edward J. McCluskey. TC, 45(11):1337-1342, 1996.

Test point insertion based on path tracingNur A. Touba, Edward J. McCluskey. vts 1996: 2-8 [doi]

Altering a Pseudo-Random Bit Sequence for Scan-Based BISTNur A. Touba, Edward J. McCluskey. itc 1996: 167-175

Applying two-pattern tests using scan-mappingNur A. Touba, Edward J. McCluskey. vts 1996: 393-399 [doi]

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