Abstract is missing.
- Manufacturability Analysis of Analog CMOS ICs through Examination of Multiple Layout SolutionsPedram Khademsameni, Marek Syrzycki. 3-11 [doi]
- Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSIArman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi. 12-19 [doi]
- Yield Estimates for the TESH Multicomputer NetworkB. M. Maziarz, V. K. Jain. 20-30 [doi]
- A Simplified Gate-Level Fault Model for Crosstalk Effects AnalysisPierluigi Civera, Luca Macchiarulo, Massimo Violante. 31-39 [doi]
- A Test-Vector Generation Methodology for Crosstalk Noise FaultsHamidreza Hashempour, Yong-Bin Kim, Nohpill Park. 40-50 [doi]
- A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption StandardGuido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri. 51-59 [doi]
- Designing Self-Checking FPGAs through Error Detection CodesCristiana Bolchini, Fabio Salice, Donatella Sciuto. 60-68 [doi]
- Self-Checking 1-out-of-n CMOS Current-Mode CheckerJimson Mathew, Elena Dubrova. 69-77 [doi]
- Partially Duplicated Code-Disjoint Carry-Skip AdderDaniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan. 78-86 [doi]
- Input Ordering in Concurrent Checkers to Reduce Power ConsumptionKartik Mohanram, Nur A. Touba. 87-98 [doi]
- New Methods for Evaluating the Impact of Single Event Transients in VDSM ICsDan Alexandrescu, Lorena Anghel, Michael Nicolaidis. 99-107 [doi]
- Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case StudiedRaoul Velazco, A. Corominas, P. Ferreyra. 108-116 [doi]
- Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate ParadigmHorng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang. 117-128 [doi]
- Scan Architecture for Shift and Capture Cycle Power ReductionPaul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici. 129-137 [doi]
- Inserting Test Points to Control Peak Power During Scan TestingRanganathan Sankaralingam, Nur A. Touba. 138-146 [doi]
- Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino CircuitsChing-Hwa Cheng. 147-158 [doi]
- Matrix-Based Test Vector Decompression Using an Embedded ProcessorKedarnath J. Balakrishnan, Nur A. Touba. 159-165 [doi]
- Data Compression for System-on-Chip Testing Using ATEFarzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi. 166-176 [doi]
- Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition FaultsJennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer. 177-185 [doi]
- Test Time Reduction in a Manufacturing Environment by Combining BIST and ATEHamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi. 186-194 [doi]
- Testing Digital Circuits with ConstraintsAhmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey. 195-206 [doi]
- On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking CircuitsCecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale. 207-215 [doi]
- Self-Checking and Fault Tolerance Quality Assessment Using Fault SamplingFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 216-224 [doi]
- A Memory Overhead valuation of the Interleaved Signature Instruction StreamFrancisco Rodríguez, José Carlos Campelo, Juan José Serrano. 225-232 [doi]
- Fault-Tolerant CAM Architectures: A Design FrameworkFabio Salice, Mariagiovanna Sami, Renato Stefanelli. 233-244 [doi]
- Using Run-Time Reconfiguration for Fault Injection in Hardware PrototypesLörinc Antoni, Régis Leveugle, Béla Fehér. 245-253 [doi]
- A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection TechniquesSara Blanc, Joaquin Gracia, Pedro J. Gil. 254-262 [doi]
- Fault List Compaction through Static Timing Analysis for Efficient Fault Injection ExperimentsMatteo Sonza Reorda, Massimo Violante. 263-274 [doi]
- Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESHSusumu Horiguchi, Yasuyuki Miura. 275-283 [doi]
- Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test ConfigurationsXiaoling Sun, A. Alimohammad, Pieter M. Trouborst. 284-292 [doi]
- Testing Layered Interconnection NetworksFabrizio Lombardi, Nohpill Park. 293-304 [doi]
- Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of FailureYuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto. 305-313 [doi]
- Yield Modeling of a WSI Telecom Router ArchitectureBing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault. 314-324 [doi]
- Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation ExploitationOzgur Sinanoglu, Alex Orailoglu. 325-333 [doi]
- Adaptive Test Scheduling in SoC s by Dynamic PartitioningDan Zhao, Shambhu J. Upadhyaya. 334-344 [doi]
- Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and RemediesThomas Verdel, Yiorgos Makris. 345-353 [doi]
- Feasibility Study of Designing TSC Sequential Circuits with 100 Fault CoverageStanislaw J. Piestrak. 354-364 [doi]
- Emulation-Based Design Errors IdentificationA. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza. 365-371 [doi]
- A New Functional Fault Model for FPGA Application-Oriented TestingMaurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 372-380 [doi]
- Neighbor Current Ratio (NCR): A New Metric for IDDQ Data AnalysisSagar S. Sabade, D. M. H. Walker. 381-389 [doi]
- CMOS Standard Cells Characterization for IDDQ TestingWitold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz. 390-398 [doi]
- On-Chip Jitter Measurement for Phase Locked LoopsTian Xia, Jien-Chung Lo. 399-407 [doi]
- Neural Networks-Based Parametric Testing of Analog ICViera Stopjaková, D. Micusík, Lubica Benusková, Martin Margala. 408-418 [doi]
- Balanced Redundancy Utilization in Embedded Memory Cores for Dependable SystemsMinsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri. 419-427 [doi]
- Repairability Evaluation of Embedded Multiple Region DRAMsY. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi. 428-436 [doi]