Stefano Di Francescantonio - researchr alias

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Viewing Publication 1 - 7 from 7

2004

Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing TestingCecilia Metra, Stefano Di Francescantonio, T. M. Mak. TC, 53(5):531-546, 2004. [doi]

2003

Automatic Modification of Sequential Circuits for Self-Checking ImplementationCecilia Metra, Stefano Di Francescantonio, Martin Omaña. dft 2003: 417-424 [doi]

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faultsCecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò. mj, 34(1):23-29, 2003. [doi]

2002

On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking CircuitsCecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale. dft 2002: 207-215 [doi]

Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line TestingCecilia Metra, Stefano Di Francescantonio, T. M. Mak. itc 2002: 100-109 [doi]

On-Chip Clock Faults DetectorCecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò. et, 18(4-5):555-564, 2002. [doi]

2001

Evaluation of Clock Distribution Networks Most Likely Faults and Produced EffectsCecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak. dft 2001: 357-365 [doi]

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