Table of Contents

• Yield Analysis of Compiler-Based Arrays of Embedded SRAMsXiaopeng Wang, Marco Ottavi, Fabrizio Lombardi. 3-10 [doi]
• Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a ChipTianxu Zhao, Xuchao Duan, Yue Hao, Peijun Ma. 11-17 [doi]
• IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale IntegrationMeng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer. 18-25 [doi]
• Calibration of Open Interconnect Yield ModelsDirk K. de Vries, Paul L. C. Simon. 26-33 [doi]
• Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse FaultsT. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri. 34 [doi]
• Level-Hybrid Optoelectronic TESH Interconnection NetworkVijay K. Jain, Glenn H. Chapman. 45-52 [doi]
• Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS)Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet. 53 [doi]
• Clock Calibration Faults and their Impact on Quality of High Performance MicroprocessorsCecilia Metra, T. M. Mak, Daniele Rossi. 63-70 [doi]
• A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAsMonica Alderighi, Fabio Casini, Sergio D Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi. 71-78 [doi]
• CodSim -- A Combined Delay Fault SimulatorWangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi. 79 [doi]
• BIST Based Fault Diagnosis Using Ambiguous Test SetHiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu. 89-96 [doi]
• On the Test and Diagnosis of the Perfect ShuffleLuca Schiano, Fabrizio Lombardi. 97-104 [doi]
• Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption StandardGuido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri. 105 [doi]
• 3DSDM: A 3 Data-Source Diagnostic MethodY. Hariri, Claude Thibeault. 117-123 [doi]
• Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog CircuitsMarco S. Dragic, Martin Margala. 124-131 [doi]
• CROWNE: Current Ratio Outliers with Neighbor EstimatorSagar S. Sabade, D. M. H. Walker. 132-139 [doi]
• Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current SensorsAbhijit Prasad, D. M. H. Walker. 140 [doi]
• ATE-Amenable Test Data Compression with No Cyclic ScanHamidreza Hashempour, Fabrizio Lombardi. 151-158 [doi]
• A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test EquipmentFengming Zhang, Young-Jun Lee, T. Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, S. Max, Phil Perkinson. 159-166 [doi]
• Function-Based Dynamic Compaction and its Impact on Test Set SizesJames Wingfield, Jennifer Dworak, M. Ray Mercer. 167-174 [doi]
• Constrained ATPG for Broadside Transition TestingXiao Liu, Michael S. Hsiao. 175 [doi]
• Test Compaction by Using Linear-Matrix Driven Scan ChainsSandeep Bhatia. 185-190 [doi]
• Multiple Scan Chain Design Technique for Power Reduction during Test Application in BISTDebjyoti Ghosh, Swarup Bhunia, Kaushik Roy. 191-198 [doi]
• Design Scan Test Strategy for Single Phase Dynamic CircuitsChing-Hwa Cheng. 199 [doi]
• Scan-Based BIST Diagnosis Using an Embedded ProcessorKedarnath J. Balakrishnan, Nur A. Touba. 209-216 [doi]
• Hybrid BIST Using an Incrementally Guided LFSRC. V. Krishna, Nur A. Touba. 217-224 [doi]
• Hybrid BIST Time Minimization for Core-Based Systems with STUMPS ArchitectureGert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin. 225 [doi]
• A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory SystemsParag K. Lala. 235-241 [doi]
• Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix SymbolsHaruhiko Kaneko, Eiji Fujiwara. 242-249 [doi]
• Quadruple Time Redundancy AddersWhitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.. 250-256 [doi]
• Error Correcting Codes for Crosstalk Effect MinimizationDaniele Rossi, S. Cavallotti, Cecilia Metra. 257 [doi]
• A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to DetectCharles F. Hawkins, Ali Keshavarzi, Jaume Segura. 267 [doi]
• Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and ImplementationYukiya Miura, Daisuke Kato. 279-286 [doi]
• An Approach for Selection of Test Points for Analog Fault DiagnosisKranthi K. Pinjala, Bruce C. Kim. 287-294 [doi]
• BiST Model for IC RF-Transceiver Front-EndJerzy Dabrowski. 295-302 [doi]
• A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal CircuitsJohn M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani. 303 [doi]
• Thermal Management of High Performance MicroprocessorsArman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi. 313-319 [doi]
• Fault Recovery Based on Checkpointing for Hard Real-Time Embedded SystemsYing Zhang, Krishnendu Chakrabarty. 320-327 [doi]
• Fault Tolerant Multi-Layer Neural Networks with GA TrainingEiko Sugawara, Masaru Fukushi, Susumu Horiguchi. 328-335 [doi]
• Detailed Comparison of Dependability Analyses Performed at RT and Gate LevelsAbdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante. 336-343 [doi]
• Low Cost Convolutional Code Based Concurrent Error Detection in FSMsKonstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos. 344-351 [doi]
• Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan ArchitectureShervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi. 352-360 [doi]
• An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal SignalsJohn M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani. 361-368 [doi]
• Fault Tolerant Hopfield Associative Memory on TorusRafic A. Ayoubi, Haissam Ziade, Magdy A. Bayoumi. 369-376 [doi]
• Efficiency of Transient Bit-Flips Detection by Software Means: A Complete StudyB. Nicolescu, P. Peronnard, Raoul Velazco, Yvon Savaria. 377-384 [doi]
• Buffer and Controller Minimisation for Time-Constrained Testing of System-On-ChipAnders Larsson, Erik Larsson, Petru Eles, Zebo Peng. 385-392 [doi]
• Regressive Testing for System-on-Chip with Unknown-Good-YieldNoh-Jin Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi. 393-400 [doi]
• Error Detection in Signed Digit Arithmetic Circuit with Parity CheckerGian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano. 401-408 [doi]
• Application-Dependent Testing of FPGA InterconnectsMehdi Baradaran Tahoori. 409-416 [doi]
• Automatic Modification of Sequential Circuits for Self-Checking ImplementationCecilia Metra, Stefano Di Francescantonio, Martin Omaña. 417-424 [doi]
• Control Constrained Resource Partitioning for Complex SoCsDan Zhao, Shambhu J. Upadhyaya, Martin Margala. 425-432 [doi]
• Partial Error Masking to Reduce Soft Error Failure Rate in Logic CircuitsKartik Mohanram, Nur A. Touba. 433 [doi]
• An Integrated Design Approach for Self-Checking FPGAsCristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia. 443-450 [doi]
• Power-Constrained Embedded Memory BIST ArchitectureBai Hong Fang, Nicola Nicolici. 451-458 [doi]
• A Memory Built-In Self-Repair for High Defect Densities Based on Error PolaritiesMichael Nicolaidis, Nadir Achouri, Lorena Anghel. 459-466 [doi]
• Redundancy, Repair, and Test Features of a 90nm Embedded SRAM GeneratorRob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker. 467-474 [doi]
• An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory ArchitectureXiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott. 475 [doi]
• Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL ModelsHamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali. 485-492 [doi]
• Preliminary Validation of an Approach Dealing with Processor ObsolescenceLorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary. 493 [doi]
• Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA CoreGang Zeng, Hideo Ito. 503-510 [doi]
• A Uni.ed SOC Test Approach Based on Test Data Compression and TAM DesignVikram Iyengar, Anshuman Chandra. 511-518 [doi]
• Embedded Compact Deterministic Test for IP-Protected CoresAdam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici. 519 [doi]
• System-Level Analysis of Fault Effects in an Automotive EnvironmentFulvio Corno, S. Tosato, P. Gabrielli. 529-536 [doi]
• Dependability Analysis of CAN Networks: An Emulation-Based ApproachJ. Pérez, Matteo Sonza Reorda, Massimo Violante. 537 [doi]
• Exploiting Instruction Redundancy for Transient Fault ToleranceToshinori Sato. 547-554 [doi]
• An Integrated Fault-Tolerant Design Framework for VLIW ProcessorsYung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai. 555-562 [doi]
• Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check CodeSobeeh Almukhaizim, Yiorgos Makris. 563-570 [doi]
• Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area OverheadVinu Vijay Kumar, John Lach. 571 [doi]
• Soft-Error Detection Using Control Flow AssertionsO. Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 581-588 [doi]
• SIED: Software Implemented Error DetectionB. Nicolescu, Yvon Savaria, Raoul Velazco. 589-596 [doi]
• Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI CircuitsAtul Maheshwari, Israel Koren, Wayne Burleson. 597 [doi]