Pedram A. Riahi - researchr alias

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Viewing Publication 1 - 5 from 5

2005

A Flow Graph Technique for DFT Controller ModificationMohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi. socc 2005: 55-60 [doi]

Simulating Faults of Combinational IP Core-based SOCs in a PLI EnvironmentPedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi. dft 2005: 389-397 [doi]

2003

The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation MethodologyPedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi. ats 2003: 274-277 [doi]

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation EnvironmentPedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi. csreaESA 2003: 139-143

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan ArchitectureShervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi. dft 2003: 352-360 [doi]

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