Table of Contents

• Outstanding Challenges in Testing Nanotechnology Based Integrated CircuitsKewal K. Saluja. 2 [doi]
• Leveraging Infrastructure IP for SoC YieldYervant Zorian. 3-5 [doi]
• Reducing Scan Shifts Using Folding Scan TreesHiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita. 6-11 [doi]
• Improving Test Quality of Scan-Based BIST by Scan Chain PartitioningDong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara. 12-17 [doi]
• IC Reliability Simulator ARET and Its Application in Design-for-ReliabilityXiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa. 18-23 [doi]
• Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance TracesZaid Al-Ars, A. J. van de Goor. 24-27 [doi]
• Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable CellsYuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka. 28-31 [doi]
• Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL ToolFabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti. 32-37 [doi]
• Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple FaultsYu-Chiun Lin, Shi-Yu Huang. 38-43 [doi]
• Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time FaultsYu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung. 44-49 [doi]
• A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM* Comparison ModelXiaofan Yang. 50-57 [doi]
• Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault ModelsTsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara. 58-63 [doi]
• On Estimation of Fault Efficiency for Path Delay FaultsMasayasu Fukunaga, Seiji Kajihara, Sadami Takeoka. 64-67 [doi]
• Software-Based Delay Fault Testing of Processor CoresVirendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara. 68-71 [doi]
• A DFT Approach for Path Delay Faults in Interconnected CircuitsIrith Pomeranz, Sudhakar M. Reddy. 72-77 [doi]
• Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time ComplexitySukanta Das, Anirban Kundu, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri. 78-83 [doi]
• A BIST Architecture for FPGA Look-Up Table Testing Reduces ReconfigurationsEhsan Atoofian, Zainalabedin Navabi. 84-89 [doi]
• A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor LogicMd. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar. 90-95 [doi]
• Domain Testing Based on Character String PredicateRuilian Zhao, Michael R. Lyu, Yinghua Min. 96-101 [doi]
• Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov ChainsMatthias Beyer, Winfried Dulz, Fenhua Zhen. 102-105 [doi]
• Efficiency Analysis and Safety Assessment of Automatic Testing for Safety-Critical SoftwareFangmei Wu, Lei Huang. 106-109 [doi]
• An Expression s Single Fault Model and the Testing MethodsYunzhan Gong, Wanli Xu, Xiaowei Li. 110-115 [doi]
• PLL Based High Speed Functional TestingJayasanker Jayabalan, Chee Kiang Goh, Ooi Ban Leong, Leong Mook Seng, Mahadevan K. Iyer, Andrew A. O. Tay. 116-119 [doi]
• Issues Related to the Formulation of DFT Solution for Analog Circuit Test Using Equivalent Fault AnalysisMike W. T. Wong. 120-123 [doi]
• A Sigma-Delta Modulation Based BIST Scheme for A/D ConvertersKuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng. 124-129 [doi]
• A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area ConstraintToshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara. 130-135 [doi]
• Optimal Scan Tree Construction with Test Vector Modification for Test CompressionKohei Miyase, Seiji Kajihara. 136-141 [doi]
• STAGE: A Decoding Engine Suitable for Multi-Compressed Test DataBernd Koenemann. 142-147 [doi]
• Automatic Design Validation Framework for HDL Descriptions via RTL ATPGLiang Zhang, Michael S. Hsiao, Indradeep Ghosh. 148-153 [doi]
• An Automatic Circuit Extractor for RTL VerificationTun Li, Yang Guo, Sikun Li. 154-160 [doi]
• An Efficient Observability Evaluation Algorithm Based on Factored Use-Def ChainsTao Lv, Jianping Fan, Xiaowei Li. 161-167 [doi]
• Delay Testing of MOS Transistor with Gate Oxide ShortMichel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand. 168-173 [doi]
• An Enhanced Test Generator for Capacitance Induced Crosstalk Delay FaultsArani Sinha, Sandeep K. Gupta, Melvin A. Breuer. 174-177 [doi]
• Delay Test Pattern Generation Considering Crosstalk-Induced EffectsHuawei Li, Yue Zhang, Xiaowei Li. 178-183 [doi]
• Automated Test Model Generation from Switch Level Custom CircuitsMagdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu. 184-189 [doi]
• Power Conscious BIST Design for Sequential Circuits Using ghost-FSMSamir Roy, Biplab K. Sikdar. 190-195 [doi]
• Average Leakage Current Macromodeling for Dual-Threshold Voltage CircuitsYongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li. 196-201 [doi]
• Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan TestOzgur Sinanoglu, Alex Orailoglu. 202-209 [doi]
• Analysis of Software Test Item Generation - Comparison between High Skilled and Low Skilled EngineersMasayuki Hirayama, Tetsuya Yamamoto, Osamu Mizuno, Tohru Kikuno. 210-215 [doi]
• Conformance Test of Distributed Transaction ServiceChang Xu, Beihong Jin. 216-219 [doi]
• Build-In-Self-Test for SoftwareShiyi Xu. 220-223 [doi]
• Testing the Conformity of Transactional Attributes of Components by SimulationHui-Qun Zhao, Qin-Xin Gao, Yuan Gao. 224-229 [doi]
• Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault InformationBaris Arslan, Alex Orailoglu. 230-235 [doi]
• Fault Diagnosis for Physical Defects of Unknown BehaviorsXiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita. 236-241 [doi]
• Fault Detection for Testable Realizations of Multiple-Valued Logic FunctionsPan Zhongliang. 242-249 [doi]
• Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address DecodersLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri. 250-255 [doi]
• Defect Oriented Fault Analysis for SRAMRei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu. 256-261 [doi]
• A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAsL. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti. 262-267 [doi]
• Between-Core Vector Overlapping for Test Cost Reduction in Core TestingTsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka. 268-273 [doi]
• The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation MethodologyPedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi. 274-277 [doi]
• A Test Generation Approach for Systems-on-Chip that Use Intellectual Property CoresZhigang Jiang, Sandeep K. Gupta. 278-283 [doi]
• Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault TestabilityHafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 284-289 [doi]
• BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault TestabilityJunhao Shi, Görschwin Fey, Rolf Drechsler. 290-293 [doi]
• Test Synthesis for Datapaths Using Datapath-Controller FunctionsMichiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara. 294-299 [doi]
• Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict AnalysisDong Xiang, Shan Gu, Hideo Fujiwara. 300-305 [doi]
• Optimal System-on-Chip Test SchedulingErik Larsson, Hideo Fujiwara. 306-311 [doi]
• SOC Test Time Minimization Under Multiple ConstraintsJulien Pouget, Erik Larsson, Zebo Peng. 312-317 [doi]
• Test Time Minimization for Hybrid BIST of Core-Based SystemsGert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin. 318-325 [doi]
• On-Chip Short-Time Interval Measurement for High-Speed Signal Timing CharacterizationTian Xia, Jien-Chung Lo. 326-331 [doi]
• An On-Chip Jitter Measurement Circuit for the PLLChin-Cheng Tsai, Chung-Len Lee. 332-335 [doi]
• A Low-Cost Jitter Measurement Technique for BIST ApplicationsJui-Jer Huang, Jiun-Lang Huang. 336-339 [doi]
• Measurement-Based Modeling with Adaptive SamplingJunfeng Wang, Jianhua Yang, Gaogang Xie, Mingtian Zhou, Zhongcheng Li. 340-347 [doi]
• Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device TestingBaosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov. 348-353 [doi]
• Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection MethodYuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer. 354-359 [doi]
• Lowering Cost of Test: Parallel Test or Low-Cost ATE?Jochen Rivoir. 360-365 [doi]
• A Processor-Based Built-In Self-Repair Design for Embedded MemoriesChin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu. 366-371 [doi]
• March SL: A Test For All Static Linked Memory FaultsSaid Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers. 372-377 [doi]
• Testing Delay Faults in Embedded CAMsXiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng. 378-383 [doi]
• Stress Test for Disturb Faults in Non-Volatile MemoriesMohammad Gh. Mohammad, Kewal K. Saluja. 384-389 [doi]
• A BIST Circuit for IDDQ TestsMasaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita. 390-395 [doi]
• At-Speed Current TestingYinghua Min, Jishun Kuang, Xiaoyan Niu. 396-399 [doi]
• IDDT ATPG Based on Ambiguous Delay AssignmentsJishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang. 400-405 [doi]
• Improvement of Detectability for CMOS Floating Gate Defects in Supply Current TestHiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo. 406-411 [doi]
• A DFT Selection Method for Reducing Test Application Time of System-on-ChipsMasahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara. 412-417 [doi]
• Sharing BIST with Multiple Cores for System-on-a-ChipHuaguo Liang, Cuiyun Jiang. 418-423 [doi]
• Designing Multiple Scan Chains for Systems-on-ChipMd. Saffat Quasem, Sandeep K. Gupta. 424-427 [doi]
• Optimizing Test Access Mechanism under Constraints by Genetic Local Search AlgorithmYingxiang Wang, Weikang Huang. 428-433 [doi]
• Test Data Volume Reduction by Test Data RealignmentIrith Pomeranz, Sudhakar M. Reddy. 434-439 [doi]
• Test Resource Partitioning Based on Efficient Response Compaction for Test Time and TesteYinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra. 440-445 [doi]
• Test Response Compression Based on Huffman CodingHideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue. 446-451 [doi]
• Probability Model for Faults in Large-Scale Multicomputer SystemsGaocai Wang, Jianer Chen, Guojun Wang, Songqiao Chen. 452-457 [doi]
• Design Retargetable Platform System for Microprocessor Functional TestLing Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji. 458-461 [doi]
• Assessing Software Implemented Fault Detection and Fault Tolerance MechanismsPiotr Gawkowski, Janusz Sosnowski. 462-467 [doi]
• Briefing a New Approach to Improve the EMI Immunity of DSP SystemsFabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum. 468-473 [doi]
• Design Error Diagnosis Based on Verification TechniquesGuanghui Li, Ming Shao, Xiaowei Li. 474-477 [doi]
• SAT-Based Algorithm of Verification for Port Order FaultMing Shao, Guanghui Li, Xiaowei Li. 478-481 [doi]
• Equivalence Checking Using Independent CutsZhan Xu, Xiaolang Yan, Yongjiang Lu, Haitong Ge. 482-487 [doi]
• A Method to Calculate the Reliability of Component-Based SoftwareYuan Zhu, Jianhua Gao. 488-491 [doi]
• An Object-Oriented Program Automatic Execute Model and the Research of AlgorithmDa-Hai Jin, Yun-Zhan Gong. 492-495 [doi]
• User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NTJin-Min Yang, Da-Fang Zhang, Xue Dong Yang. 496-501 [doi]
• RTL Concurrent Fault SimulationLi Shen. 502 [doi]
• Property Classification for Functional Verification BasedMing Zhu, Jinian Bian, Weimin Wu, Hongxi Xue. 503 [doi]
• Error Detection and Correction in VLSI Systems by Online Testing and RetryingJian-Hui Jiang. 504 [doi]
• Testability Improvement During High-Level SynthesisSaeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir. 505 [doi]
• A Test Architecture for System-on-a-ChipYong-sheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye. 506 [doi]
• Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BISTHe Hu 0002, Yihe Sun. 507 [doi]
• Test Pattern Length Required to Reach the Desired Fault CoverageJunichi Hirase. 508 [doi]
• Damage Size and Software Safety Demonstration Stress TestingZhongwei Xu, Bangxing Chen. 509 [doi]
• Study on the Cost/Benefit/Optimization of Software Safety TestMeng Li, Zhu Xu. 510 [doi]