Michiaki Muraoka - researchr alias

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Viewing Publication 1 - 19 from 19

2014

A critical net reshape-router for high-performance VLSI layout designYusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga. apccas 2014: 587-590 [doi]

2013

A multilayer crosstalk avoidance router using restricted maze gridsYoshiya Fujii, Michiaki Muraoka, Masahiko Toyonaga. mwscas 2013: 641-644 [doi]

2004

A DFT Selection Method for Reducing Test Application Time of System-on-ChipsMasahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara. ieicet, 87-D(3):609-619, 2004. [doi]

Design methodology for SoC arthitectures based on reusable virtual coresMichiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada. aspdac 2004: 256-262 [doi]

2003

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area ConstraintToshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara. ats 2003: 130-135 [doi]

A DFT Selection Method for Reducing Test Application Time of System-on-ChipsMasahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara. ats 2003: 412-417 [doi]

VCDS tool demonstrationRafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka. aspdac 2003: 459 [doi]

VCore-based design methodologyMichiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida. aspdac 2003: 441-445 [doi]

Synthesis for SoC architecture using VCoresHiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada. aspdac 2003: 446-452 [doi]

VCore-based platform for SoC designYoichi Onishi, Michiaki Muraoka, Makoto Utsuki, Naoyuki Tsubaki. aspdac 2003: 453-458 [doi]

2002

A SoC Test Strategy Based on a Non-Scan DFT MethodHiroshi Date, Toshinori Hosokawa, Michiaki Muraoka. ats 2002: 305-310 [doi]

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path CircuitsToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka. vts 2002: 328-335 [doi]

A State Reduction Method for Non-Scan Based FSM Testing with Don t Care Inputs Identification TechniqueToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka. ats 2002: 55-60 [doi]

1997

A Partial Scan Design Method Based on n-Fold Line-up StructuresToshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu. ats 1997: 306 [doi]

1996

A Design for testability Method Using RTL PartitioningToshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka. ats 1996: 88-93 [doi]

1995

Design for testability using register-transfer level partial scan selectionAkira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka. aspdac 1995: [doi]

1993

A State Traversal Algorithm Using a State Covariance MatrixAkira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin. dac 1993: 97-101 [doi]

1985

ACTAS: an accurate timing analysis system for VLSIMichiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa. dac 1985: 152-158 [doi]

1982

Logic simulation for LSIKazuyuki Hirakawa, Noboru Shiraki, Michiaki Muraoka. dac 1982: 755-761 [doi]

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