Abstract is missing.
- Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola s Microprocessors Based on PowerPC(tm) Instruction Set ArchitectureNandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich. 3-8 [doi]
- Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs Amit R. Pandey, Janak H. Patel. 9-15 [doi]
- Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 ProcessorDilip K. Bhavsar, Richard A. Davies. 16-24 [doi]
- Very Low Voltage Testing of SOI Integrated CircuitsEric MacDonald, Nur A. Touba. 25-30 [doi]
- Performance Comparison of VLV, ULV, and ECR TestsWanli Jiang, Erik Peterson. 31-36 [doi]
- Experimental Results for Slow-Speed TestingChao-Wen Tseng, James Li, Edward J. McCluskey. 37-42 [doi]
- Innovations in Test AutomationJ. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski. 43-46 [doi]
- Scan-Path with Directly Duplicated and Inverted Duplicated RegistersMichael Gössel, Egor S. Sogomonyan, Adit D. Singh. 47-52 [doi]
- An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential CircuitsAiman El-Maleh, Ali Al-Suwaiyan. 53-59 [doi]
- Logic BIST and Scan Test Techniques for Multiple Identical BlocksKarim Arabi. 60-68 [doi]
- Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron TechnologiesRobert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch. 69-74 [doi]
- Yield-Reliability Modeling: Experimental Verification and Application to Burn-In ReductionThomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy. 75-80 [doi]
- Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in ReductionSagar S. Sabade, D. M. H. Walker. 81-86 [doi]
- A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required?Lee Song, Rudy Garcia, Andrew Levy, Donald L. Wheater. 87-90 [doi]
- How Effective are Compression Codes for Reducing Test Data Volume?Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina. 91-96 [doi]
- Test Vector Compression Using EDA-ATE SynergiesAjay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra. 97-102 [doi]
- On Test Data Volume Reduction for Multiple Scan Chain DesignsSudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz. 103-110 [doi]
- Spectrum-Based BIST in Complex SOCsGanapathy Kasturirangan, Michael S. Hsiao. 111-116 [doi]
- A Self Calibrated ADC BIST MethodologyHung-kai Chen, Chih-hu Wang, Chau-chin Su. 117-122 [doi]
- Self-Testing Second-Order Delta-Sigma Modulators Using Digital StimulusChee-Kian Ong, Kwang-Ting (Tim) Cheng. 123-128 [doi]
- A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution?Bill Bottoms, Lee Song, Paul Patton, Wilhelm Radermacher. 129-132 [doi]
- Testing High-Speed SoCs Using Low-Speed ATEsMehrdad Nourani, James Chin. 133-138 [doi]
- Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCsMadhu K. Iyer, Kwang-Ting Cheng. 139-144 [doi]
- On Using Efficient Test Sequences for BISTRené David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 145-152 [doi]
- Controlling Peak Power During Scan TestingRanganathan Sankaralingam, Nur A. Touba. 153-159 [doi]
- Test Vector Modification for Power Reduction during Scan TestingSeiji Kajihara, Koji Ishida, Kohei Miyase. 160-165 [doi]
- Test Power Reduction through Minimization of Scan Chain TransitionsOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu. 166-172 [doi]
- Wireless TestRobert C. Aitken, Mustapha Slamani, H. Ding, William R. Eisenstadt, Sanghoon Choi, John Mclaughlin. 173-174 [doi]
- Analog and Mixed Signal BIST: Too Much, Too Little, Too Late?Adam Osseiran, William De Wilkins, Barry Baril, Sassan Tabatabaei, Fidel Muradali, Ken Posse, Lee Song. 175-176 [doi]
- Test as a Key Enabler for Faster Yield Ramp-UpJulie Segal, Rene Segers, Rob Aitken, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman. 177-180 [doi]
- Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential CircuitsEnamul Amyeen, Irith Pomeranz, W. Kent Fuchs. 181-186 [doi]
- Diagnosis of Sequence-Dependent ChipsChien-Mo James Li, Edward J. McCluskey. 187-192 [doi]
- Speeding Up The Byzantine Fault Diagnosis Using Symbolic SimulationShi-Yu Huang. 193-200 [doi]
- Filters Designed for Testability Wrapped on the Mixed-Signal Test BusJosé Vicente Calvano, Vladimir Castro Alves, Antônio C. Mesquita, Marcelo Lubaszewski. 201-206 [doi]
- Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency DivisionTakahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha. 207-212 [doi]
- Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance AnalysisSule Ozev, Alex Orailoglu. 213-222 [doi]
- Instruction-Based Self-Testing of Processor CoresNektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian. 223-228 [doi]
- An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and ValidationLuis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López. 229-236 [doi]
- Program Slicing for Hierarchical Test GenerationVivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra. 237-246 [doi]
- Design for Testability and Testing of IEEE 1149.1 Tap ControllerSubhasish Mitra, Edward J. McCluskey, Samy Makar. 247-252 [doi]
- On Using Rectangle Packing for SOC Wrapper/TAM Co-OptimizationVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. 253-258 [doi]
- Cluster-Based Test Architecture Design for System-on-ChipSandeep Kumar Goel, Erik Jan Marinissen. 259-264 [doi]
- Multi-GigaHertz Testing Challenges and SolutionsKarim Arabi, Klaus-Dieter Hilliges, David C. Keezer, Sassan Tabatabaei. 265-268 [doi]
- Exploiting Dominance and Equivalence using Fault TuplesKumar N. Dwarakanath, R. D. (Shawn) Blanton. 269-274 [doi]
- Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham. 275-280 [doi]
- RAMSES-FT: A Fault Simulator for Flash Memory Testing and DiagnosticsKuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu. 281-288 [doi]
- Eigen-Signatures for Regularity-based IDDQ TestingYukio Okuda. 289-294 [doi]
- Speeding-Up IDDQ MeasurementsClaude Thibeault. 295-301 [doi]
- Dynamic Supply Current Testing of Analog Circuits Using Wavelet TransformSwarup Bhunia, Kaushik Roy. 302-310 [doi]
- Debating the Future of Burn-InEdward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers. 311-314 [doi]
- Beyond CMOSB. Courtoi, M. Forshaw. 315-316 [doi]
- Challenges of Mixed-Signal Board Design and TestG. Roberts. 317-320 [doi]
- A Method of Test Generation for Path Delay Faults in Balanced Sequential CircuitsSatoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa. 321-327 [doi]
- A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path CircuitsToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka. 328-335 [doi]
- Test Pattern Generation for Signal Integrity Faults on Long InterconnectsAmir Attarha, Mehrdad Nourani. 336-344 [doi]
- Improved Test Monitor Circuit in Power Pin DfTRodger Schuttert, Frans de Jong, Ben Kup. 345-350 [doi]
- Measuring Stray Capacitance on Tester HardwareAchintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley. 351-356 [doi]
- Power Supply Transient Signal Analysis Under Real Process and Test Hardware ModelsAbhishek Singh, Jim Plusquellic, Anne E. Gattiker. 357-366 [doi]
- Layout Analysis to Extract Open Nets Caused by Systematic Failure MechanismsSreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah. 367-372 [doi]
- Fault Models for Speed Failures Caused by Bridges and OpensSreejit Chakravarty, Ankur Jain. 373-378 [doi]
- Timed Test Generation Crosstalk Switch Failures in Domino CMOS CircuitsRahul Kundu, R. D. (Shawn) Blanton. 379-388 [doi]
- Testing and Diagnosing Embedded Content Addressable MemoriesJin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu. 389-394 [doi]
- Testing Static and Dynamic Faults in Random Access MemoriesSaid Hamdioui, Zaid Al-Ars, A. J. van de Goor. 395-400 [doi]
- Approximating Infinite Dynamic Behavior for DRAM Cell DefectsZaid Al-Ars, A. J. van de Goor. 401-406 [doi]
- Validation and Test of Network Processors and ASICsC.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim. 407-410 [doi]
- Test Economics for Multi-site Test with Modern Cost Reduction TechniquesErik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges. 411-416 [doi]
- LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and InterconnectsKrishna Sekar, Sujit Dey. 417-422 [doi]
- Useless Memory Allocation in System-on-a-Chip Test: Problems and SolutionsPaul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici. 423-432 [doi]
- Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip EvaluationDiego Vázquez, Gloria Huertas, Gildas Leger, Adoración Rueda, José L. Huertas. 433-438 [doi]
- Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical SystemsVincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet. 439-444 [doi]
- Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark. 445-446 [doi]
- Challenges in Nanometric Technology Scaling: Trends and ProjectionsJaume Segura, Vivek De, Ali Keshavarzi. 447-448 [doi]
- SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim. 449-450 [doi]