An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits

Aiman El-Maleh, Ali Al-Suwaiyan. An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. In 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It s a Gamble, 28 April - 2 May 2002, Monterey, CA, USA. pages 53-59, IEEE Computer Society, 2002. [doi]

Abstract

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