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Viewing Publication 1 - 47 from 47

2025

Test, Debug, and Repair for Chiplet-Based DesignsAnshuman Chandra, Esteban Garita-Rodríguez, Pradipta Ghosh. vts 2025: 1 [doi]

Testing Functional Interfaces And Complex PADs Within Multi-Die Packages With IEEE P3405Anshuman Chandra, Nir Sever, Martin Keim. ets 2025: 1-4 [doi]

DFT Techniques For Efficient 3D IC Interconnect Test For Chiplet and Multi-Die PackageAnshuman Chandra, Chi-Chun Yang, Quoc Phan, Martin Keim. ets 2025: 1-6 [doi]

2024

2023

A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT ImplementationAnshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora. itc 2023: 11-20 [doi]

2015

Designing efficient combinational compression architecture for testing industrial circuitsAnshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur. vdat 2015: 1-6 [doi]

Designing effective scan compression solutions for industrial circuitsSubramanian Chebiyam, Anshuman Chandra, Rohit Kapur. isqed 2015: 167-172 [doi]

2014

Unifying scan compressionSwapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan. dft 2014: 191-196 [doi]

2013

Special session 11B: Hot topic on-chip clocking - Industrial trendsAnshuman Chandra. vts 2013: 1 [doi]

2011

Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur. ats 2011: 432-437 [doi]

3D-Scalable Adaptive Scan (3D-SAS)Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur. 3dic 2012: 1-6 [doi]

2009

Scalable Adaptive Scan (SAS)Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa. date 2009: 1476-1481 [doi]

Proactive management of X s in scan chains for compressionAnshuman Chandra, Yasunari Kanzawa, Rohit Kapur. isqed 2009: 260-265 [doi]

2008

2007

2006

Response compaction for system-on-a-chip based on advanced convolutional codesYinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra. chinaf, 49(2):262-272, 2006. [doi]

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codesYinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra. tim, 55(2):389-399, 2006. [doi]

2005

2004

2003

Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) CodesAnshuman Chandra, Krishnendu Chakrabarty. TC, 52(8):1076-1088, 2003. [doi]

A unified approach to reduce SOC test data volume, scan power and testing timeAnshuman Chandra, Krishnendu Chakrabarty. tcad, 22(3):352-363, 2003. [doi]

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and TesteYinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra. ats 2003: 440-445 [doi]

A Unified Approach for SOC Testing Using Test Data Compression and TAM OptimizationVikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty. date 2003: 11188-11190 [doi]

A Uni.ed SOC Test Approach Based on Test Data Compression and TAM DesignVikram Iyengar, Anshuman Chandra. dft 2003: 511-518 [doi]

2002

Test Resource Partitioning for System-on-a-ChipKrishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra. Volume 20 of Frontiers in electronic testing, Kluwer / Springer, 2002. [doi]

Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data CompressionAnshuman Chandra, Krishnendu Chakrabarty. date 2002: 598-603 [doi]

Reduction of SOC test data volume, scan power and testing time using alternating run-length codesAnshuman Chandra, Krishnendu Chakrabarty. dac 2002: 673-678 [doi]

How Effective are Compression Codes for Reducing Test Data Volume?Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina. vts 2002: 91-96 [doi]

Low-power scan testing and test data compression forsystem-on-a-chipAnshuman Chandra, Krishnendu Chakrabarty. tcad, 21(5):597-604, 2002. [doi]

Test data compression and decompression based on internal scanchains and Golomb codingAnshuman Chandra, Krishnendu Chakrabarty. tcad, 21(6):715-722, 2002. [doi]

2001

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb codingAnshuman Chandra, Krishnendu Chakrabarty. date 2001: 145-149 [doi]

Combining Low-Power Scan Testing and Test Data Compression for System-on-a-ChipAnshuman Chandra, Krishnendu Chakrabarty. dac 2001: 166-169 [doi]

Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data CompressionAnshuman Chandra, Krishnendu Chakrabarty. vts 2001: 42-47 [doi]

Efficient Test Application for Core-Based Systems Using Twisted-Ring CountersAnshuman Chandra, Krishnendu Chakrabarty, Mark C. Hansen. vlsi, 2001(4):475-486, 2001. [doi]

Test Resource Partitioning for SOCsAnshuman Chandra, Krishnendu Chakrabarty. dt, 18(5):80-91, 2001. [doi]

System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codesAnshuman Chandra, Krishnendu Chakrabarty. tcad, 20(3):355-368, 2001. [doi]

2000

Test Data Compression for System-on-a-Chip Using Golomb CodesAnshuman Chandra, Krishnendu Chakrabarty. vts 2000: 113-120 [doi]

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Publications by 'Anshuman Chandra'

Viewing Publication 1 - 47 from 47

2025

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2023

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2014

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2011

2009

2008

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2006

2005

2004

2003

2002

2001

2000

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