Table of Contents

• Off-Chip Super-Resolution AI Model to Support Embedded Memory DiagnosisSimone Anedda, Paolo Bernardi 0002, Matteo Coppetta, Giorgio Insinga, Tommaso Montedoro, Annachiara Ruospo, Rudolf Ullmann, Felix Tengler. 1-6 [doi]
• Oscillation-Based Test for mm-Wave Reflection-Type Phase ShiftersMarc Margalef-Rovira, Loïc Vincent, Emmanuel Pistono, Sylvain Bourdel, Manuel J. Barragán, Philippe Ferrari. 1-6 [doi]
• Scalable Design-for-Calibration of Programmable Silicon PhotonicsLawrence M. Schlitt, Priyank Kalla, Steve Blair. 1-6 [doi]
• A Holistic Framework to Assess Reliability Issues in Emerging Technologies due to Ageing, Voltage and Temperature VariationSara Mannaa, Grégory Loubet, Salvatore Pappalardo, Cédric Marchand 0002, Damien Deleruyelle, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Yifan Wang, François Marc, Chhandak Mukherjee, Marina Deng, Cristell Maneux, Ian O'Connor. 1-6 [doi]
• A Single-Cycle, Area-Efficient Calibration Method for TDC-based Timing MonitorsMadiha A. Sheikh, Marco Ottavi. 1-6 [doi]
• Radiation Hardened and Self-Recoverable Latch Design for Quad-Node Upset MitigationEvangelos Paparsenos, Yiorgos Tsiatouhas. 1-4 [doi]
• Soft-Error Sensitivity Analysis of Adder Tree architectures for Compute-In-Memory AcceleratorsPanagiotis Chaidos, Alexis Maras, Georgios Alexandris, Dimitrios Soudris, Sotirios Xydis. 1-4 [doi]
• Sample-efficient Performance Tuning of mixed-signal ASICs via Probabilistic SurrogatesTim Strobel, Nima Shahpari, Sarah Rottacker, Roland Rösslhuber, Jens Anders. 1-6 [doi]
• TDDB Stress Test Coverage Quantification using Cell-aware Transistor State Stress ModelVladimir A. Zivkovic, Stephan Eggersglüß, Andreas Glowatz, Daniel Tille. 1-6 [doi]
• Shaping the Future of Multi-Die Stacking: Overcoming Challenges through Collaboration and StandardsSandeep Kumar Goel. 1 [doi]
• Memory ECC Logic Testing using MBISTWei Zou, Artur Pogiel, Martin Keim, Albert Au, Jongsin Yun, Luc Romain. 1-4 [doi]
• Fault Model-Driven Formal Verification of Cryptographic Hardware Against Fault AttacksDaniel Thirion, George-Cristian Sercaianu, Valentin Egloff, Jean-Marc Daveau, Vincent Beroulle, David Hély, Philippe Roche. 1-6 [doi]
• Machine Learning Approach for Cross-Technology Prediction of the Generated Single Event TransientKonstantinos Varakliotis, Nikolaos Zazatis, Marko S. Andjelkovic, Nikolaos Chatzivangelis, Fabian Vargas 0001, Milos Krstic, Christos P. Sotiriou. 1-4 [doi]
• Exploring Hybrid Brain-Inspired Architectures and Technology Heterogeneity for High Performance AI Applications: Challenges & SolutionsLetícia Maria Bolzani Pöhls. 1-6 [doi]
• CODA: Confidence-Driven Adaptive Testing of Analog/Mixed-Signal Circuits Using Gaussian Mixture ModelsAnkush, Ashiqur Rasul, Anurup Saha, Abhijit Chatterjee. 1-6 [doi]
• STA-Based Single Event Transient Propagation in Advanced Technology NodesNikolaos Chatzivangelis, Marios Karagiannis, Christos Georgakidis, Nikolaos Sketopoulos, Marko S. Andjelkovic, Luigi Dilillo, Christos P. Sotiriou. 1-4 [doi]
• Special Session: Hardware Security at the Circuit and Layout LevelsSajjad Parvin, Carl Riehm, Nan Du 0004, Ralf Brederlow, Frank Sill Torres, Rolf Drechsler. 1-8 [doi]
• A CIM-based Gaussian Random Number Generator for Edge Devices as Security PrimitiveFouwad Jamil Mir, Asmae El Arrassi, Said Hamdioui, Mottaqiallah Taouil. 1-4 [doi]
• SWEET-DREAM: Side-Channel Weakness Evaluation and Enhanced Mitigation for DREAM-CIMFouwad Jamil Mir, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil. 1-6 [doi]
• Test Sample Ranking for Fault Detection in Decision Tree-based Inference ModelAntonio Emmanuele, Mario Barbareschi, Alberto Bosio. 1-6 [doi]
• FAT-SNN: Fault-Aware Training of Flexible Analog Spiking Neural Networks Using Robust SurrogatesSimon Schupp, Tara Gheshlaghi, Priyanjana Pal, Mehdi B. Tahoori. 1-6 [doi]
• Shooting Neutrons at Neurons: Radiation Testing of a Spiking Neural Network on Flash-Based FPGAsWim Nijsink, Bruno Endres Forlin, Amirreza Yousefzadeh, Marco Ottavi. 1-4 [doi]
• Hardware Trojans Horses: Two Decades Later, What We Really KnowGiorgio Di Natale, Emanuele Valea. 1-10 [doi]
• Actuarial Voltage Scaling (AVS+): A Statistical Reliability Framework for Reducing Guardbands in Systolic ArraysLarisa Goffman-Vinopal. 1-4 [doi]
• Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided VerificationYonghao Wang, Jiaxin Zhou, Yang Yin, Hongqin Lyu, Zhiteng Chao, Wenchao Ding 0007, Jing Ye 0001, Tiancheng Wang, Huawei Li 0001. 1-6 [doi]
• Bridging the Speed-Accuracy Gap: Layout-Aware Pre-Silicon Side-Channel AnalysisAsmaa Kassimi, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil. 1-4 [doi]
• Leading-Edge Test Technology and Strategies for Automotive ProductsKazuyuki Iwaguro. 1 [doi]
• Exploration of Reference Trimming Schemes for STT-MRAMsPei Yun Lin, Jin-Fu Li 0001. 1-4 [doi]
• Robustness Assessment of Edge AI-Based Li-Ion Battery State-Of-Health PredictionAlexandru Ciobotaru, Cosmina Corches, Dan Gota, Szilárd Enyedi, Ovidiu Stan, Liviu Miclea. 1-6 [doi]
• Design-for-Testability and Built-In Self-Test Techniques for SRAM-Based Compute-In-Memory SystemsShyue-Kung Lu, Chin-Jung Lee. 1-4 [doi]
• On Evaluating the Security of TRNG-driven SRAM Scrambling ArchitectureManan Kumar Singh, Gaurav Kumar 0001, Kashvi Bansal, Yamuna Prasad, Satyadev Ahlawat. 1-6 [doi]
• Efficient Hash-to-Index via Rejection Sampling for Online Fault Detection with Bloom/Cuckoo FiltersElijah Seth Cishugi, Kuan-Hsun Chen, Marco Ottavi. 1-6 [doi]
• Reliability, Test, and Security of Compute-In-MemoriesSoyed Tuhin Ahmed, Krishnendu Chakrabarty, Jin-Fu Li 0001, Mottaqiallah Taouil, Fouwad Jamil Mir, Said Hamdioui, Mehdi B. Tahoori, Martin Keim, Jongsin Yun. 1-9 [doi]
• Gremlins in the Silicon: Why Faulty Chips are Escaping the Fab and Crashing in the FieldMottaqiallah Taouil, R. D. Shawn Blanton, Phil Nigh, Adit D. Singh, Said Hamdioui. 1-10 [doi]
• ARMOR: Architectural Reliability via Multi-Objective Optimization for Early-Exit Neural NetworksMichalis Kontos, Georgios Konstantinidis 0003, Theocharis Theocharides, Maria K. Michael. 1-4 [doi]
• Distributed Delay-Based BIST for Mixed-Signal Circuits in Flexible ElectronicsPaula Carolina Lozano Duarte, Sule Ozev, Mehdi B. Tahoori. 1-4 [doi]
• How Testing must change in the age of AI processors, Silent Data Corruption Failures and 100s of ChipletsPhil Nigh. 1 [doi]
• An interpretable data-driven framework for variable group selection in high-dimensional manufacturing test dataYang Yang, Bin Yang 0009, Yiwen Liao Data. 1-6 [doi]
• An Elmore Delay Model Based Test Method for Post-Bond TSVsZhicheng Shao, Xiaole Cui, Xiaoxin Cui. 1-6 [doi]
• Testing of a 12 bit SARA And Cand Analog ScanAnthony Coyette, Wim Dobbelaere, Doina Dima, Arlind Billa, Krzysztof Jurga, Vladimir Zivkovic, Stephen Sunter. 1-6 [doi]
• Attacks Exploiting On-Chip Instruments and IJTAG ProtectionJoel Åhlund, Fanny Lundberg, Markus Törmänen, Erik Larsson. 1-4 [doi]
• Towards Resilient Transformer-Encoders: Fault Injection and Hardware Agnostic Error MitigationVishal Thomas, Ussama Zahid, Giulio Gambardella, Sumeet Sapkal, Haralampos-G. Stratigopoulos, Brian Clerkin. 1-4 [doi]
• Exploiting Near-Memory Computing Resources for Native, Adaptive, and Low-Overhead MBISTSabrina Ait Belkacem, Lila Ammoura, Maria Ramirez-Corrales, Marie-Lise Flottes, Patrick Girard 0001, Jean-Philippe Noel, Arnaud Virazel. 1-4 [doi]
• TDsReCAM: Time-Domain sensing for reliable ReRAM-based Content Addressable MemoryHaneen G. Hezayyin, Mahta Mayahinia, Mehdi B. Tahoori, Sule Ozev. 1-6 [doi]
• An Enhanced, Self-Adapting Asynchronous Interface for High-Frequency IJTAG Instruments In Clock Mesh EnvironmentsLuc Romain, Katarzyna Wojnowska, Roger Mah, Albert Au, Wei Zou, Martin Keim. 1-6 [doi]
• Fast Circuit Analysis via Neighborhood-Guided Maximum Common SubgraphPaolo Bernardi 0002, Lorenzo Cardone, Stefano Quer. 1-6 [doi]
• Beyond Fingerprints: Systematic Design of APUFs for Batch IdentificationLina Baolati, Wenjing Rao, Natasha Devroye. 1-4 [doi]
• A Chosen-Ciphertext Side-Channel Attack on Protected ML-KEM Using Pairwise Bit-FlippingRuize Wang, Linus Backlund, Elena Dubrova. 1-6 [doi]
• Encoded Repair Configuration Chains for Die-to-Die Interconnect Test and Repair LanguageAshish Reddy Bommana, Anshuman Chandra, Moiz Khan. 1-4 [doi]
• Hierarchical EMFI Analysis on a RISC-V SoCDillibabu Shanmugam, Zhenyuan Liu 0005, Patrick Schaumont. 1-4 [doi]
• Discovering Unknown Wafermap Patterns Using Cluster-Graph-Based AnalyticsQiang Guo, Zixin Shen, Hongliang Lü, Liangliang Yu, Chunlin Ren, Junlin Huang. 1-4 [doi]
• Advances in Testing and Reliability BenchmarksFrancesco Angione, Paolo Bernardi 0002, Nicola Di Gruttola Giardino, Gabriele Filipponi, Giusy Iaria, Giacomo Perlo, Irith Pomeranz, Antonio Porsia, Annachiara Ruospo, Ernesto Sánchez 0001, Vittorio Turco. 1-10 [doi]
• A Ferroelectric nvSRAM PUF with Built-In Grey Bit Masking based on FeCAP-SRAM InteractionsLucas Rhetat, Jean-Philippe Noel, Bastien Giraud, Laurent Grenouillet, Cédric Marchand 0002, Ian O'Connor. 1-6 [doi]
• Path Delay Fault Testable KFDD Circuits with Polynomial Test Pattern GenerationMartha Schnieber, Rolf Drechsler. 1-4 [doi]
• Auto-Generating Ageing Self-Tests with Hardware in the Loop for Commercial MicrocontrollersLeandro Lanzieri, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt. 1-4 [doi]
• Re-sequencing ECC and Built-In Self-Repair with In-Page Fault Scrambling for Enhancing Yield and Reliability of Flash MemoryShyue-Kung Lu, Qian-Rui Dong. 1-4 [doi]
• SOLDER: State-Space Oriented Learning with Denoising-Enhanced Representations for PCB Defect AnalysisMd Fahim Ul Islam, Krishnendu Chakrabarty. 1-4 [doi]
• EXACT: Edge-eXplainable Autonomous Causal Telemetry for Silicon Lifecycle ManagementHsiao-Ping Ni, Eduardo Ortega, Krishnendu Chakrabarty. 1-6 [doi]
• Impact and Characterization of Single Event Failures in Hyperdimensional Computing Hardware AcceleratorMarcello Barbirotta, Marco Angioli, Rocco Martino, Federico Frontera, Antonio Mastrandrea, Mauro Olivieri. 1-4 [doi]
• A real opportunity or still a promise? The current status of the RISC-V ecosystemElia Lazzeri, Gianluca Furano, Luca Cassano. 1-9 [doi]
• Exploration of Machine Learning-Based Test Methodologies in High-Volume Manufacturing RF TestingHakan Cetin, Alexandre Leon, Manuel J. Barragán, Philippe Ferrari. 1-6 [doi]
• Using Analog IJTAG to Measure ISO 26262 MetricsBartlomiej Praselski, Stephen Sunter. 1-6 [doi]
• A Circular Repair Scheme for 3DIC Die-to-Die InterconnectsAnshuman Chandra, Moiz Khan, Barbara Dzialowska, Marta Stepniewska. 1-6 [doi]
• Extending FPGA-based NRZ Test Signals Beyond 100 GbpsDavid C. Keezer, Cao Wang, Shengbo Liu, Xiaochun Li, Yindong Xiao. 1-6 [doi]
• NURSE: A Distributed Architecture for Runtime Fault Management in Processor DesignsAshwin Santhosh, Artur Jutman, Endri Kaja, Wolfgang Ecker, Maksim Jenihhin. 1-4 [doi]
• Use of GitHub Copilot Agent Mode for Automated Development in R&D Data EngineeringMarco D'Acunzo, Daniele Rossi, Jamal Mohamad Maamoun, Giorgia Cassetta. 1-4 [doi]
• Structural Testing Methodology for Deep Neural Networks based on RRAMEmmanouil Anastasios Serlis, Emmanouil Arapidis, Theofilos Spyrou, Anteneh Gebregiorgis, Mottaqiallah Taouil, Said Hamdioui, Moritz Fieback. 1-4 [doi]
• Introduction to Post Quantum Cryptography for Resource Constrained SystemsLeonidas Kosmidis, Sergi Alcaide, Matina Maria Trompouki, Antonio Escobar-Molero, Adam Anglart, Daniel Van Geest, Martin Zuber, Jean-Paul Truong, Andrej Grebenc, Detlef Houdeau. 1-7 [doi]