Artur Jutman - researchr alias

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Viewing Publication 1 - 57 from 57

2024

2023

On-Chip Sensors Data Collection and Analysis for SoC Health ManagementKonstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov. dft 2023: 1-6 [doi]

2019

2017

2016

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan ArchitecturesIgor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin. et, 32(3):245-255, 2016. [doi]

On coverage of timing related faults at board levelArtur Jutman, Igor Aleksejev, Sergei Devadze. ets 2016: 1-2 [doi]

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCsKonstantin Shibin, Sergei Devadze, Artur Jutman. latw 2016: 69-74 [doi]

A suite of IEEE 1687 benchmark networksAnton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath. itc 2016: 1-10 [doi]

2015

Virtual reconfigurable scan-chains on FPGAs for optimized board testIgor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin. latw 2015: 1-6 [doi]

No Fault Found: The root causeErik Larsson, Bill Eklow, Scott Davidsson, Rob Aitken, Artur Jutman, Christophe Lotz. vts 2015: 1 [doi]

2014

2013

Effective Scalable IEEE 1687 Instrumentation Network for Fault ManagementArtur Jutman, Sergei Devadze, Konstantin Shibin. dt, 30(5):26-35, 2013. [doi]

On in-system programming of non-volatile memoriesAnton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski. mixdes 2013: 408-413 [doi]

2012

2011

2010

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital CircuitsDmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. dsd 2010: 658-663 [doi]

Testing beyond the SoCs in a lego styleAnton Tsertov, Artur Jutman, Sergei Devadze. ewdts 2010: 334-338 [doi]

Parallel X-fault simulation with critical path tracing techniqueRaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. date 2010: 879-884 [doi]

Structural fault collapsing by superposition of BDDs for test generation in digital circuitsRaimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman. isqed 2010: 250-257 [doi]

Fast Fault Simulation for Extended Class of Faults in Scan Path CircuitsRaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. delta 2010: 14-19 [doi]

Fault collapsing with linear complexity in digital circuitsRaimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman. iscas 2010: 653-656 [doi]

2009

2008

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocolsTomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng. iet-cdt, 2(6):445-460, 2008. [doi]

Calculation of LFSR Seed and Polynomial Pair for BIST ApplicationsArtur Jutman, Anton Tsertov, Raimund Ubar. ddecs 2008: 275-278 [doi]

Reseeding using compaction of pre-generated LFSR sub-sequencesArtur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar. icecsys 2008: 1290-1295 [doi]

DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital CircuitsWitold A. Pleskacz, Viera Stopjaková, Tomasz Borejko, Artur Jutman, Andrzej Wakanis. tie, 55(6):2405-2415, 2008. [doi]

Parallel fault backtracing for calculation of fault coverageRaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. aspdac 2008: 667-672 [doi]

2007

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDsRaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. emnets 2007: 131-136 [doi]

Learning Digital Test and Diagnostics via InternetRaimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke. ijoe, 3(1), 2007. [doi]

2006

2005

An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime PlatformArtur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov. dsdm 2005: 412-419 [doi]

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDsJaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman. edcc 2005: 332-344 [doi]

2004

Asynchronous e-learning resources for hardware design issuesArtur Jutman, Alexander Sudnitson, Raimund Ubar, Heinz-Dietrich Wuttke. compsystech 2004: 1-6 [doi]

At-speed on-chip diagnosis of board-level interconnect faultsArtur Jutman. ets 2004: 2-7 [doi]

2002

Practical works for on-line teaching design and test of digital circuitsArtur Jutman, Raimund Ubar, Vladimir Hahanov, O. Skvortsova. icecsys 2002: 1223-1226 [doi]

Fast static compaction of tests composed of independent sequences: basic properties and comparison of methodsJaan Raik, Artur Jutman, Raimund Ubar. icecsys 2002: 445-448 [doi]

2001

Timing simulation of digital circuits with binary decision diagramsRaimund Ubar, Artur Jutman, Zebo Peng. date 2001: 460-466 [doi]

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Publications by 'Artur Jutman'

Viewing Publication 1 - 57 from 57

2024

2023

2019

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2016

2015

2014

2013

2012

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