Abstract is missing.
- A jitter separation and BER estimation method for asymmetric total jitter distributionsMasahiro Ishida, Kiyotaka Ichiyama. 1-9 [doi]
- Low cost dynamic error detection in linearity testing of SAR ADCsNimit Jain, Nitin Agarwal, Rajavelu Thinakaran, Rubin A. Parekhji. 1-8 [doi]
- Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCsT. Kogan, Y. Abotbol, G. Boschi, Gurgen Harutyunyan, I. Kroul, H. Shaheen, Yervant Zorian. 1-6 [doi]
- Advancing test compression to the physical dimensionKrishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox. 1-10 [doi]
- Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test setSubhadip Kundu, Kuldip Kumar, Rishi Kumar, Rohit Kapur. 1-7 [doi]
- Highly reliable and low-cost symbiotic IOT devices and systemsBing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu. 1-10 [doi]
- Software-based online self-testing of network-on-chip using bounded model checkingYing Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang. 1-10 [doi]
- Run-time hardware trojan detection using performance countersRana Elnaggar, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 1-10 [doi]
- Automotive keynote: Look Mom! No hands!Joachim Kunkel. 1 [doi]
- A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systemsShuo-Lian Hong, Kuen-Jong Lee. 1-10 [doi]
- Non-intrusive detection of defects in mixed-signal integrated circuits using light activationBaris Esen, Anthony Coyette, Nektar Xama, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen. 1-7 [doi]
- Cognitive approach to support dynamic aging compensationSouhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, David Meyer, Sylvie Naudet, A. Jain, C. R. Parthasarathy, Alain Bravaix. 1-7 [doi]
- Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statisticsValentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo. 1-9 [doi]
- Fault simulation acceleration for TRAX dictionary construction using GPUsMatthew Beckler, Ronald D. Blanton. 1-9 [doi]
- Use models for extending IEEE 1687 to analog testPeter Sarson, Jeff Rearick. 1-8 [doi]
- Cross-layer refresh mitigation for efficient and reliable DRAM systems: A comparative studyXiaoan Ding, Xi Liang, Yanjing Li. 1-10 [doi]
- DFM-aware fault model and ATPG for intra-cell and inter-cell defectsArani Sinha, Sujay Pandey, Ayush Singhal, Alodeep Sanyal, Alan Schmaltz. 1-10 [doi]
- Exploiting path delay test generation to develop better TDF tests for small delay defectsAnkush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja. 1-10 [doi]
- Full-scan LBIST with capture-per-cycle hybrid test pointsSylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada. 1-9 [doi]
- RTL functional test generation using factored concolic executionSonal Pinto, Michael S. Hsiao. 1-10 [doi]
- Safety analysis for integrated circuits in the context of hybrid systemsV. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur. 1-10 [doi]
- Increasing IJTAG bandwidth and managing security through parallel locking-SIBsSaurabh Gupta, Al Crouch, Jennifer Dworak, Daniel Engels. 1-10 [doi]
- A/MS benchmark circuits for comparing fault simulation, DFT, and test generation methodsStephen Sunter, Peter Sarson. 1-7 [doi]
- Frequency scaled segmented (FSS) scan architecture for optimized scan-shift power and faster test application timeW. Pradeep, P. Narayanan, R. Mittal, N. Maheshwari, N. Naresh. 1-10 [doi]
- Security keynote: Ultra-low-energy security circuit primitives for IoT platformsSanu Mathew. 1 [doi]
- High throughput multiple device diagnosis systemSameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula. 1-10 [doi]
- Kernel based clustering for quality improvement and excursion detectionNik Sumikawa, Matt Nero, Li-C. Wang. 1-10 [doi]
- Single-pin test control for Big A, little D devicesMichael Laisne, Hans Martin von Staudt, Sourabh Bhalerao, Mark Eason. 1-10 [doi]
- Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedureSrikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen. 1-9 [doi]
- Layout-aware 2-step window-based pattern reordering for fast bridge/open test generationMasayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki. 1-8 [doi]
- Accurate and robust spectral testing with relaxed instrumentation requirementsYuming Zhuang, Degang Chen. 1-10 [doi]
- An effective functional safety solution for automotive systems-on-chipG. Tshagharyan, Gurgen Harutyunyan, Yervant Zorian. 1-10 [doi]
- Symbol-based health-status analysis in a core router systemShi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
- Thwarting analog IC piracy via combinational lockingJiafan Wang, Congyin Shi, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu. 1-10 [doi]
- Testing beyond the green lightBob Klosterboer. 1 [doi]
- Modeling trans-threshold correlations for reducing functional test time in ultra-low power systemsChristopher J. Lukas, Farah B. Yahya, Benton H. Calhoun. 1-10 [doi]
- Changepoint-based anomaly detection in a core router systemShi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
- An on-chip ADC BIST solution and the BIST enabled calibration schemeXiankun Jin, Tao Chen, Mayank Jain, Arun Kumar Barman, David Kramer, Doug Garrity, Randall L. Geiger, Degang Chen. 1-10 [doi]
- Fault tolerant electronic system designBoyang Du, Luca Sterpone. 1-6 [doi]
- Demystifying automotive safety and security for semiconductor developerV. Prasanth, David Foley, Srivaths Ravi. 1-10 [doi]
- Analysis and mitigation or IR-Drop induced scan shift-errorsStefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen. 1-8 [doi]
- Some considerations on choosing an outlier method for automotive product linesLi-C. Wang, Sebastian Siatkowski, Chuanhe Jay Shan, Matthew Nero, Nikolas Sumikawa, LeRoy Winemberg. 1-10 [doi]
- Analytical test of 3D integrated circuitsRaphael Robertazzi, Micheal Scheurman, Matt Wordeman, Shurong Tian, Christy Tyberg. 1-10 [doi]
- Design-for-test and test time optimization for 3D SOCsSurajit Kumar Roy, Chandan Giri. 1-10 [doi]
- Front-end layout reflection for test chip designZeye Dexter Liu, Phillip Fynan, Ronald D. Blanton. 1-10 [doi]
- Accurate ADC testing with significantly relaxed instrumentation including large cumulative jitterLi Xu, Yuming Zhuang, Rajavelu Thinakaran, Kenneth M. Butler, Degang Chen. 1-10 [doi]
- Systematic defect detection methodology for volume diagnosis: A data mining perspectiveChuanhe Jay Shan, Pietro Babighian, Yan Pan, John M. Carulli, Li-C. Wang. 1-10 [doi]
- Selecting target bridging faults for uniform circuit coverageIrith Pomeranz. 1-7 [doi]
- Hardware trojan detection through information flow security verificationAdib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark Tehranipoor. 1-10 [doi]
- On applying scan based structural test for designs with dual-edge triggered flip-flopsXijiang Lin. 1-8 [doi]
- Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimizationSabyasachi Deyati, Barry J. Muldrey, Byunghoo Jung, Abhijit Chatterjee. 1-10 [doi]
- Automated die inking: A pattern recognition-based approachConstantinos Xanthopoulos, Peter Sarson, Heinz Reiter, Yiorgos Makris. 1-6 [doi]
- Built-in self-test for stability measurement of low dropout regulatorJae-woong Jeong, Ender Yilmaz, LeRoy Winemberg, Sule Ozev. 1-9 [doi]
- Marginal PCB assembly defect detection on DDR3/4 memory busSergei Odintsov, Artur Jutman, Sergei Devadze. 1-10 [doi]
- POSTT: Path-oriented static test compaction for transition faults in scan circuitsIrith Pomeranz. 1-8 [doi]
- Maximizing scan pin and bandwidth utilization with a scan routing fabricYan Dong, Grady Giles, Guoliang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood. 1-10 [doi]