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2026

Advances in Testing and Reliability BenchmarksFrancesco Angione, Paolo Bernardi 0002, Nicola Di Gruttola Giardino, Gabriele Filipponi, Giusy Iaria, Giacomo Perlo, Irith Pomeranz, Antonio Porsia, Annachiara Ruospo, Ernesto Sánchez 0001, Vittorio Turco. ets 2026: 1-10 [doi]

Reverse Steepening of a Fault Coverage CurveIrith Pomeranz. tcad, 45(1):557-561, January 2026. [doi]

Buffered Bounded Transparent Scan for Test GenerationIrith Pomeranz. access, 14:94357-94368, 2026. [doi]

Aging Aware Steepening of the Fault Coverage Curve of a Single Functional Test SequenceIrith Pomeranz. access, 14:92298-92308, 2026. [doi]

Test Generation for Subcircuits With High-Functional Switching ActivitiesIrith Pomeranz. access, 14:25082-25092, 2026. [doi]

Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive FaultsIrith Pomeranz. tcad, 45(5):2275-2279, May 2026. [doi]

Minimal Set of Primary Input Vector Pairs for Two-Cycle Gate-Exhaustive FaultsIrith Pomeranz. access, 14:50204-50215, 2026. [doi]

Modular Functional Test Sequences for Test CompactionIrith Pomeranz. tcad, 45(1):407-417, January 2026. [doi]

Functionally Undetectable Interconnect Faults in Chiplet-Based DesignsIrith Pomeranz. todaes, 31(5), September 2026. [doi]

Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test SetIrith Pomeranz. todaes, 31(3), May 2026. [doi]

Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan ChainIrith Pomeranz. todaes, 31(2), March 2026. [doi]

Aging Aware Test Generation Procedure for Multicycle Scan-Based TestsIrith Pomeranz. access, 14:27125-27136, 2026. [doi]

Late Breaking Results - Test Selection for In-Field Testing Using a Two-Dimensional Aging SpaceIrith Pomeranz, Subashini Gopalsamy, Arani Sinha, Yonsang Cho. vts 2026: 1-3 [doi]

Late Breaking Results - Diagnostic Test Templates for Two-Cycle Gate-Exhaustive FaultsIrith Pomeranz. vts 2026: 1-3 [doi]

Late Breaking Results - Close-to-Functional Tests for Two-Cycle Interconnect FaultsIrith Pomeranz. vts 2026: 1-3 [doi]

2025

Hazard-Based Functionally Possible Transition Faults With High Functional Switching ActivitiesIrith Pomeranz. tcad, 44(12):4818-4827, December 2025. [doi]

Sequential Test Generation and Design-for-Testability With Preferred Interconnect CubesIrith Pomeranz. access, 13:214668-214678, 2025. [doi]

Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-TestIrith Pomeranz. tcad, 44(8):3241-3245, August 2025. [doi]

Diagnostic Test Compaction of Functional Test SequencesIrith Pomeranz. access, 13:174776-174788, 2025. [doi]

Direct Search Procedure for Functional Compaction With Improved Fault CoverageIrith Pomeranz. tcad, 44(5):1981-1990, May 2025. [doi]

Test Templates to Guide Test Generation for Single-Cycle Gate-Exhaustive FaultsIrith Pomeranz. todaes, 30(3), May 2025. [doi]

COCO: Configuration-Based Compaction of a Compressed Topped-Off Test SetIrith Pomeranz. tcad, 44(5):1991-1999, May 2025. [doi]

Chip Aging and Transition Faults With High Switching Activities Under Scan-Based TestsIrith Pomeranz. tvlsi, 33(7):2014-2018, July 2025. [doi]

Arranging a Pool of Functional Test Sequences for Variable In-Field Test PeriodsIrith Pomeranz. access, 13:10009-10021, 2025. [doi]

Functionally-Possible Subcircuit-Based Tests for Path Delay FaultsIrith Pomeranz. access, 13:29801-29809, 2025. [doi]

DTGx2: Dual Target Diagnostic Test GenerationIrith Pomeranz. todaes, 30(4), July 2025. [doi]

Retry-Based Synchronization for Online Testing of Identical Logic BlocksIrith Pomeranz. tvlsi, 33(5):1447-1451, May 2025. [doi]

SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard ScanIrith Pomeranz. todaes, 30(1):1-13, 2025. [doi]

DYCOCO: Dynamic Configuration-Based Test CompactionIrith Pomeranz. access, 13:91025-91033, 2025. [doi]

Close-to-Functional Simulation-Model-Based Tests for Single-Cycle Interconnect FaultsIrith Pomeranz. access, 13:179475-179483, 2025. [doi]

Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test SequencesIrith Pomeranz. vts 2025: 1-7 [doi]

Chip Aging and Double Transition FaultsIrith Pomeranz. vts 2025: 1-7 [doi]

Functional Logic Diagnosis with Observation Points on Next-State VariablesIrith Pomeranz. itc 2025: 402-405 [doi]

Functional Synchronization for Online Testing of Identical Logic BlocksIrith Pomeranz. dft 2025: 1-6 [doi]

Timing-Verification Test Generation Targeting Small Delay DefectsJiezhong Wu, Nilanjan Mukherjee 0001, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski. vts 2025: 1-7 [doi]

2024

Generating Storage-Aware Test Sets Targeting Several Fault ModelsHari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman. isvlsi 2024: 15-20 [doi]

Delay Monitoring Under Different PVT Corners for Test and Functional OperationHari Addepalli, Jiezhong Wu, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski. itc 2024: 157-166 [doi]

A Storage Based LBIST Scheme for Logic DiagnosisSubashini Gopalsamy, Irith Pomeranz. vts 2024: 1-7 [doi]

Generation of Two-Cycle Tests for Structurally Similar CircuitsJerin Joe, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski. tcad, 43(2):694-703, February 2024. [doi]

Weak and Strong Non-Robust Tests for Functionally Possible Path Delay FaultsIrith Pomeranz. access, 12:156651-156661, 2024. [doi]

Bit-Complemented Test Data to Replace the Tail of a Fault Coverage CurveIrith Pomeranz. tvlsi, 32(4):609-618, April 2024. [doi]

Unconstrained-Activation Functional-Detection Scan-Based TestsIrith Pomeranz. tcad, 43(12):4860-4864, December 2024. [doi]

Functional Compaction for Functional Test SequencesIrith Pomeranz. access, 12:98130-98140, 2024. [doi]

Two-dimensional Search Space for Extracting Broadside Tests from Functional Test SequencesIrith Pomeranz. todaes, 29(3), May 2024. [doi]

Test Generation for Functionally Possible SubpathsIrith Pomeranz. tcad, 43(12):4841-4851, December 2024. [doi]

Test Insertion for Dynamic Test CompactionIrith Pomeranz. tcad, 43(4):1302-1306, April 2024. [doi]

Longest Path Selection Based on Path IdentifiersIrith Pomeranz. access, 12:14512-14520, 2024. [doi]

Functionally Possible Path Delay Faults With High Functional Switching ActivityIrith Pomeranz, Yervant Zorian. tvlsi, 32(11):2159-2163, November 2024. [doi]

Dynamic Test Compaction of a Compressed Test Set Shared Among Logic BlocksIrith Pomeranz. tcad, 43(1):394-402, January 2024. [doi]

Testability Evaluation for Local Design ModificationsIrith Pomeranz. tvlsi, 32(1):195-199, January 2024. [doi]

Reduced On-chip Storage of Seeds for Built-in Test GenerationIrith Pomeranz. todaes, 29(3), May 2024. [doi]

Conventional Tests for Approximate Scan LogicIrith Pomeranz. dt, 41(3):5-13, June 2024. [doi]

Sharing of Topped-Off Compressed Test Sets Among Logic BlocksIrith Pomeranz. access, 12:49895-49903, 2024. [doi]

Functional Design-for-Testability for Functional Test SequencesIrith Pomeranz. tcad, 43(12):4852-4859, December 2024. [doi]

Test Compaction Using (k, 1)-Cycle TestsIrith Pomeranz. vts 2024: 1-7 [doi]

Functionally-Possible Gate-Exhaustive Bridging FaultsIrith Pomeranz. itc 2024: 31-35 [doi]

2023

Fully Deterministic Storage Based Logic Built-In Self-TestSubashini Gopalsamy, Irith Pomeranz. vts 2023: 1-7 [doi]

Topping Off Test Sets Under Bounded Transparent ScanIrith Pomeranz. tcad, 42(1):341-345, 2023. [doi]

Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed TestsIrith Pomeranz. tvlsi, 31(9):1259-1268, September 2023. [doi]

Storage-Based Logic Built-In Self-Test With Cyclic TestsIrith Pomeranz. tcad, 42(9):3118-3122, September 2023. [doi]

Path Unselection for Path Delay Fault Test GenerationIrith Pomeranz. tvlsi, 31(2):267-275, February 2023. [doi]

Sharing of Compressed Tests Among Logic BlocksIrith Pomeranz. tvlsi, 31(4):421-430, April 2023. [doi]

Diagnostic Test Point Insertion and Test CompactionIrith Pomeranz. tvlsi, 31(2):276-285, February 2023. [doi]

Test Data Compression for Transparent-Scan SequencesIrith Pomeranz. tvlsi, 31(4):601-605, April 2023. [doi]

Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test SetIrith Pomeranz. tcad, 42(4):1336-1345, April 2023. [doi]

Dummy Faulty Units for Reduced Fail Data Volume From Logic FaultsIrith Pomeranz. tvlsi, 31(11):1754-1762, November 2023. [doi]

Partially Specified Output Response for Reduced Fail Data VolumeIrith Pomeranz. tcad, 42(9):3123-3127, September 2023. [doi]

Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive FaultsIrith Pomeranz. tcad, 42(8):2752-2760, 2023. [doi]

Storage and Counter Based Logic Built-In Self-TestIrith Pomeranz. access, 11:139335-139344, 2023. [doi]

Compact Set of Functional Broadside Tests with Fault Detection on Primary OutputsIrith Pomeranz. vts 2023: 1-7 [doi]

Expanding a Pool of Functional Test Sequences to Support Test CompactionIrith Pomeranz. vts 2023: 1-7 [doi]

Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation LinesIrith Pomeranz. itc 2023: 105-110 [doi]

2022

Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied TestsHari Addepalli, Irith Pomeranz. glvlsi 2022: 345-349 [doi]

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate FaultsHari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman. ats 2022: 120-125 [doi]

Test Generation for an Iterative Design Flow with RTL ChangesJerin Joe, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski. itc 2022: 305-313 [doi]

Fast Test Generation for Structurally Similar CircuitsJerin Joe, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski. vts 2021: 1-7 [doi]

Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive FaultsIrith Pomeranz. tcad, 41(12):5635-5643, 2022. [doi]

Preponing Fault Detections for Test Compaction Under Transparent ScanIrith Pomeranz. tvlsi, 30(10):1543-1547, 2022. [doi]

GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive FaultsIrith Pomeranz. tcad, 41(7):2315-2322, 2022. [doi]

Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive FaultsIrith Pomeranz. tcad, 41(3):776-783, 2022. [doi]

Storage-Based Logic Built-in Self-Test With Multicycle TestsIrith Pomeranz. tcad, 41(10):3553-3557, 2022. [doi]

Functional Test Sequences as a Source for Partially Functional Launch-on-Shift TestsIrith Pomeranz. tvlsi, 30(11):1803-1807, 2022. [doi]

Pass/Fail Data for Logic Diagnosis Under Bounded Transparent ScanIrith Pomeranz. tcad, 41(11):4862-4872, 2022. [doi]

Multicycle Tests With Fault Detection Test Data for Improved Logic DiagnosisIrith Pomeranz. tcad, 41(5):1587-1591, 2022. [doi]

Increasing the Fault Coverage of a Truncated Test SetIrith Pomeranz. todaes, 27(6), 2022. [doi]

Static Test Compaction Using Independent Suffixes of a Transparent-Scan SequenceIrith Pomeranz. tcad, 41(4):1130-1141, 2022. [doi]

Test Sequences for Faults in the Scan LogicIrith Pomeranz. tvlsi, 30(10):1568-1572, 2022. [doi]

Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault ModelsIrith Pomeranz. itc 2022: 474-478 [doi]

Two-Dimensional Test Generation ObjectiveIrith Pomeranz. ats 2022: 108-113 [doi]

Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered LinesIrith Pomeranz. ats 2022: 114-119 [doi]

Compaction of Compressed Bounded Transparent-Scan Test SetsIrith Pomeranz. glvlsi 2022: 339-343 [doi]

Storage-Based Logic Built-In Self-Test with Variable-Length Test DataIrith Pomeranz. dft 2022: 1-6 [doi]

Usable Circuits with Imperfect Scan LogicIrith Pomeranz. ats 2022: 156-161 [doi]

2021

Logic Diagnosis with Hybrid Fail DataIrith Pomeranz, M. Enamul Amyeen. todaes, 26(3), 2021. [doi]

Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data VolumeIrith Pomeranz, M. Enamul Amyeen. tcad, 40(8):1711-1720, 2021. [doi]

Storage-Based Built-In Self-Test for Gate-Exhaustive FaultsIrith Pomeranz. tcad, 40(10):2189-2193, 2021. [doi]

Maximal Independent Fault Set for Gate-Exhaustive FaultsIrith Pomeranz. tcad, 40(3):598-602, 2021. [doi]

PRESERVE: Static Test Compaction that Preserves Individual Numbers of TestsIrith Pomeranz. tcad, 40(4):803-807, 2021. [doi]

Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input VectorsIrith Pomeranz. todaes, 26(4), 2021. [doi]

Covering Test Holes of Functional Broadside TestsIrith Pomeranz. todaes, 26(3), 2021. [doi]

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