Table of Contents

• Session details: Session 5B: VLSI Design + VLSI Circuits and Power Aware Design 2Swaroop Ghosh. [doi]
• Session details: Session 3B: VLSI for Machine Learning and Artifical Intelligence 1Jingtong Hu. [doi]
• Session details: Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided DesignSai Manoj Pudukotai Dinakarrao. [doi]
• Session details: Session 6B: Special Session - 2: Application-oriented Hardware Security Challenges and SolutionsHassan Salmani. [doi]
• Session details: Session 2B: Computer-Aided Design (CAD)Emre Salman. [doi]
• Session details: Session 3A: VLSI Design + VLSI Circuits and Power Aware Design 1Saraju Mohanty. [doi]
• Session details: Session 5A: Hardware SecurityKris Gaj. [doi]
• Session details: Session 4B: VLSI for Machine Learning and Artifical Intelligence 2Jingtong Hu. [doi]
• Session details: Session 4A: Testing, Reliability and Fault ToleranceMark Zwolinski. [doi]
• Session details: Session 1B: Emerging Computing and Post-CMOS TechnologiesDeliang Fan. [doi]
• Session details: Session 7B: Microelectronic Systems EducationBrian Skromme. [doi]
• Session details: Session 6A: Special Session -1: Machine Learning and Hardware AttacksQiaoyan Yu. [doi]
• Session details: Session 1A: Hardware SecurityKris Gaj. [doi]
• Session details: Session 2A: Hardware SecurityKris Gaj. [doi]
• AI/ML, Optimization and EDA in the TILOS AI Research InstituteAndrew B. Kahng. 1 [doi]
• Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage AssessmentPantea Kiaei, Zhenyuan Liu, Patrick Schaumont. 3-8 [doi]
• Protected ECC Still Leaks: A Novel Differential-Bit Side-channel Power Attack on ECDH and CountermeasuresTianhong Xu, Cheng Gongye, Yunsi Fei. 9-14 [doi]
• Side-Channel Analysis of the Random Number Generator in STM32 MCUsKalle Ngo, Elena Dubrova. 15-20 [doi]
• Watermarked ReRAM: A Technique to Prevent Counterfeit Memory ChipsFarah Ferdaus, Bashir Mohammad Sabquat Bahar Talukder, Md. Tauhidur Rahman. 21-26 [doi]
• Deep Neural Network and Transfer Learning for Accurate Hardware-Based Zero-Day Malware DetectionZhangying He, Amin Rezaei 0001, Houman Homayoun, Hossein Sayadi. 27-32 [doi]
• A Novel 2T2R CR-based TCAM Design for High-speed and Energy-efficient ApplicationsKangqiang Pan, Amr M. S. Tosson, Ningxuan Wang, Norman Y. Zhou, Lan Wei. 33-38 [doi]
• MnM: A Fast and Efficient Min/Max Searching in MRAMAmitesh Sridharan, Fan Zhang, Deliang Fan. 39-44 [doi]
• A Scalable, Deterministic Approach to Stochastic ComputingYadu Kiran, Marc D. Riedel. 45-51 [doi]
• Graph Neural Network based Netlist Operator Detection under Circuit RewritingGuangwei Zhao, Kaveh Shamsi. 53-58 [doi]
• Exploration into the Explainability of Neural Network Models for Power Side-Channel AnalysisAnupam Golder, Ashwin Bhat, Arijit Raychowdhury. 59-64 [doi]
• iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction OperationsShien Zhu, Shiqing Li, Weichen Liu. 65-70 [doi]
• A Memristor-based Secure Scan Design against the Scan-based Side-Channel AttacksMengqiang Lu, Aijiao Cui, Yan Shao, Gang Qu 0001. 71-76 [doi]
• Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective CapacitanceDimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, George I. Stamoulis. 77-83 [doi]
• Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC ExplorationM. Imtiaz Rashid, Benjamin Carrion Schafer. 85-90 [doi]
• A Scheduling Framework for Decomposable Kernels on Energy Harvesting IoT Edge NodesSethu Jose, John Sampson, Vijaykrishnan Narayanan, Mahmut Taylan Kandemir. 91-96 [doi]
• Efficient Cross-Level Processor Verification using Coverage-guided FuzzingNiklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler. 97-103 [doi]
• On Attacking Locking SIB based IJTAG ArchitectureGaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat. 105-109 [doi]
• Protecting Deep Neural Network Intellectual Property with Architecture-Agnostic Input ObfuscationBrooks Olney, Robert Karam. 111-115 [doi]
• Inter-Architecture Portability of Artificial Neural Networks and Side Channel AttacksManoj Gopale, Gregory Ditzler, Roman Lysecky, Janet Roveda. 117-121 [doi]
• GAUR: Genetic Algorithm based Unlocking of Register Transfer Level LockingGagan Gayari, Chandan Karfa, Prithwijit Guha. 123-126 [doi]
• Distributed Logic Encryption: Essential Security Requirements and Low-Overhead ImplementationRaheel Afsharmazayejani, Hossein Sayadi, Amin Rezaei 0001. 127-131 [doi]
• An Oracle-Less Machine-Learning Attack against Lookup-Table-based Logic LockingKaveh Shamsi, Guangwei Zhao. 133-137 [doi]
• Hardware Trojan Insertion Using Reinforcement LearningAmin Sarihi, Ahmad Patooghy, Peter Jamieson, Abdel-Hameed A. Badawy. 139-142 [doi]
• LaBaNI: Layer-based Noise Injection Attack on Convolutional Neural NetworksTolulope A. Odetola, Faiq Khalid, Syed Rafay Hasan. 143-146 [doi]
• ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural AttacksArmin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet, Akash Kumar 0001. 147-151 [doi]
• RAFeL - Robust and Data-Aware Federated Learning-inspired Malware Detection in Internet-of-Things (IoT) NetworksSanket Shukla, Gaurav Kolhe, Houman Homayoun, Setareh Rafatirad, Sai Manoj P. D.. 153-157 [doi]
• Efficient Method for Timing-based Information Flow Verification in Hardware DesignsKhitam M. Alatoun, Ranga Vemuri. 159-163 [doi]
• Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access RefinementZhongdong Qi, Jingchong Zhang, Gengjie Chen, Hailong You. 165-168 [doi]
• An Efficient Maze Routing Algorithm for Fast Global RoutingZhaoqi Fu, Wenxin Yu, Jie Ma, Xin Cheng. 169-172 [doi]
• Optimal Region-based Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area ConstraintsJie Ma, Wenxin Yu, Zhaoqi Fu, Xin Cheng. 173-176 [doi]
• GAN-Dummy Fill: Timing-aware Dummy Fill Method using GANMyong Kong, Daeyeon Kim, Minhyuk Kweon, Seokhyeong Kang. 177-181 [doi]
• RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-VLucas Klemmer, Manfred Schlägl, Daniel Große. 183-187 [doi]
• Evolutionary Standard Cell Synthesis of Unconventional DesignsPrashanth H. C, Madhav Rao. 189-192 [doi]
• Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual PrototypePascal Pieper, Vladimir Herdt, Rolf Drechsler. 193-197 [doi]
• Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar ArrayVarun Bhatnagar, Gopal Raut, Santosh Kumar Vishvakarma. 199-202 [doi]
• In-Memory Computing based Machine Learning Accelerators: Opportunities and ChallengesKaushik Roy. 203-204 [doi]
• RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel BuffersKamil Khan, Sudeep Pasricha, Ryan Gary Kim. 205-210 [doi]
• DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip NetworksRose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose. 211-216 [doi]
• SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memoriesN. S. Aswathy, Sreesiddesh Bhavanasi, Arnab Sarkar, Hemangee K. Kapoor. 217-222 [doi]
• Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell ArraysHalima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza. 223-228 [doi]
• Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the EdgeTongxin Yang, Tomoaki Ukezono, Toshinori Sato. 229-235 [doi]
• P3S: A High Accuracy Probabilistic Prediction Processing System for CNN AccelerationHang Xiao, Haobo Xu, Xiaoming Chen, Yujie Wang, Yinhe Han. 237-242 [doi]
• Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning StrategyTianyang Yu, Bi-Wu, Ke Chen 0018, Chenggang Yan, Weiqiang Liu. 243-248 [doi]
• Error Resilient In-Memory Computing Architecture for CNN Inference on the EdgeMarco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza. 249-254 [doi]
• A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS TechnologyAibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui 0004, Yong Zhou, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. 255-260 [doi]
• Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace ApplicationsAibin Yan, Zhihui He, Jing Xiang, Jie Cui, Yong Zhou, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen. 261-266 [doi]
• Radiation Hardening by Design Techniques for the Mutual Exclusion ElementMoisés Herrera, Peter A. Beerel. 267-273 [doi]
• An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation TechniqueWei Xiong, Yanze Li, Changpeng Sun, Huanlin Luo, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu. 275-280 [doi]
• HDnn-PIM: Efficient in Memory Design of Hyperdimensional Computing with Feature ExtractionArpan Dutta, Saransh Gupta, Behnam Khaleghi, Rishikanth Chandrasekaran, Weihong Xu, Tajana Rosing. 281-286 [doi]
• Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow ImplementationJiaqi Yang, Hao Zheng 0005, Ahmed Louri. 287-292 [doi]
• Energy-Efficient In-SRAM Accumulation for CMOS-based CNN AcceleratorsWanqian Li, Yinhe Han, Xiaoming Chen. 293-298 [doi]
• KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and InferenceJun Zeng, Mingyang Kou, Hailong Yao. 299-304 [doi]
• A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum ComputersSuryansh Upadhyay, Abdullah Ash-Saki, Rasit Onur Topaloglu, Swaroop Ghosh. 305-308 [doi]
• Would Magnonic Circuits Outperform CMOS Counterparts?Abdulqader Nael Mahmoud, Nicoleta Cucu Laurenciu, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui. 309-313 [doi]
• An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic CircuitsZiying Cui, Ke Chen 0018, Bi-Wu, Chenggang Yan, Weiqiang Liu. 315-318 [doi]
• MRAM-based Analog Sigmoid Function for In-memory ComputingMd Hasibul Amin, Mohammed Elbtity, Mohammadreza Mohammadi, Ramtin Zand. 319-323 [doi]
• MEGA-MAC: A Merged Accumulation based Approximate MAC Unit for Error Resilient ApplicationsVishesh Mishra, Sparsh Mittal, Saurabh Singh, Divy Pandey, Rekha Singhal. 325-328 [doi]
• IoT-enabled Soft Robotics for Electrical EngineersPrabha Sundaravadivel, Prosenjit Kumar Ghosh, Bikal Suwal. 329-332 [doi]
• Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace ApplicationsAibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. 333-338 [doi]
• Compaction of Compressed Bounded Transparent-Scan Test SetsIrith Pomeranz. 339-343 [doi]
• Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied TestsHari Addepalli, Irith Pomeranz. 345-349 [doi]
• LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural NetworksAmin Shafiee, Sanmitra Banerjee, Krishnendu Chakrabarty, Sudeep Pasricha, Mahdi Nikdast. 351-355 [doi]
• Flexible and Personalized Learning for Wearable Health Applications using HyperDimensional ComputingSina Shahhosseini, Yang Ni, Emad Kasaeyan Naeini, Mohsen Imani, Amir M. Rahmani, Nikil D. Dutt. 357-360 [doi]
• An Event Based Gesture Recognition System Using a Liquid State Machine AcceleratorJingwei Zhu, Lei Wang, Xun Xiao, Zhijie Yang, Ziyang Kang, Shiming Li, LingHui Peng. 361-365 [doi]
• A Silicon Photonic Accelerator for Convolutional Neural Networks with Heterogeneous QuantizationFebin Sunny, Mahdi Nikdast, Sudeep Pasricha. 367-371 [doi]
• IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion PlanningLingyi Huang, Xiao Zang, Yu Gong, Chunhua Deng, Jingang Yi, Bo Yuan 0001. 373-377 [doi]
• MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3DSamuel J. Engers, Cheng Chu, Dawen Xu 0002, Ying Wang, Fan Chen. 379-382 [doi]
• Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control ApplicationsAdam Z. Foshie, Charles Rizzo, Hritom Das, Chaohui Zheng, James S. Plank, Garrett S. Rose. 383-386 [doi]
• HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph AnalyticsLong Tan, Mingyu Yan, Xiaochun Ye, Dongrui Fan. 387-391 [doi]
• CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main MemoriesArijit Nath, Hemangee K. Kapoor. 393-396 [doi]
• PrGEMM: A Parallel Reduction SpGEMM AcceleratorChien-Fu Chen, Mikko H. Lipasti. 397-401 [doi]
• Attack-Resistant Circuit Technologies for sub-5nm Secure Computing PlatformsSanu K. Mathew. 403 [doi]
• HELPSE: Homomorphic Encryption-based Lightweight Password Strength Estimation in a Virtual Keyboard SystemMichael Cho, Keewoo Lee, Sunwoong Kim. 405-410 [doi]
• Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive CagingRuchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi. 411-416 [doi]
• A Semi-formal Information Flow Validation for Analyzing Secret Asset Propagation in COTS IC Integrated SystemsXingyu Meng, Mahmudul Hasan 0012, Kanad Basu, Tamzidul Hoque. 417-422 [doi]
• MI2D: Accelerating Matrix Inversion with 2-Dimensional Tile ManipulationsLingfeng Chen, Tian Xia, Wenzhe Zhao, Pengju Ren. 423-429 [doi]
• Design and Evaluation of In-Exact Compressor based Approximate MultipliersPrashanth H. C, Soujanya S. R, Bindu G. Gowda, Madhav Rao. 431-436 [doi]
• LEAD: Logarithmic Exponent Approximate Divider For Image Quantization ApplicationOmkar G. Ratnaparkhi, Madhav Rao. 437-442 [doi]
• Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES ImplementationsYadi Zhong, Ujjwal Guin. 443-448 [doi]
• The Improved COTD Technique for Hardware Trojan Detection in Gate-level NetlistHassan Salmani. 449-454 [doi]
• Hands-On Teaching of Hardware Security for Machine LearningAshley Calhoun, Erick Ortega, Ferhat Yaman, Anuj Dubey, Aydin Aysu. 455-461 [doi]
• Security Aspects of Quantum Machine Learning: Opportunities, Threats and DefensesSatwik Kundu, Swaroop Ghosh. 463-468 [doi]
• Hardware Security in Advanced ManufacturingMohammad Mezanur Rahman Monjur, Joshua Calzadillas, Mashrafi Kajol, Qiaoyan Yu. 469-474 [doi]
• Resiliency in Connected Vehicle Applications: Challenges and Approaches for Security ValidationSrivalli Boddupalli, Richard Owoputi, Chengwei Duan, Tashfique Choudhury, Sandip Ray. 475-480 [doi]
• Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC PlatformsWeimin Fu, Honggang Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz, Xiaolong Guo. 481-486 [doi]
• Ran$Net: An Anti-Ransomware Methodology based on Cache Monitoring and Deep LearningXiang Zhang, Ziyue Zhang, Ruyi Ding, Cheng Gongye, Aidong Adam Ding, Yunsi Fei. 487-492 [doi]
• RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing AnalysisTanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Seyed Aresh Beheshti Shirazi, Ali Mirzaeian, Xiaojie Guo 0002, Sai Manoj P. D., Houman Homayoun, Ioannis Savidis, Liang Zhao 0002, Avesta Sasan. 493-500 [doi]
• CAD-FSL: Code-Aware Data Generation based Few-Shot Learning for Efficient Malware DetectionSreenitha Kasarapu, Sanket Shukla, Rakibul Hassan, Avesta Sasan, Houman Homayoun, Sai Manoj P. D.. 507-512 [doi]
• Survey of Machine Learning for Electronic Design AutomationKevin Immanuel Gubbi, Sayed Aresh Beheshti-Shirazi, Tyler David Sheaves, Soheil Salehi, Sai Manoj P. D., Setareh Rafatirad, Avesta Sasan, Houman Homayoun. 513-518 [doi]
• Embedded Systems Education in the 2020s: Challenges, Reflections, and Future DirectionsSudeep Pasricha. 519-524 [doi]
• A Tutorial-style Single-cycle Fast Fourier Transform ProcessorAlec Vercruysse, M. Weston Miller, Joshua Brake, David M. Harris. 525-530 [doi]
• Enhancing Information Security Courses With a Remotely Accessible Side-Channel Analysis SetupAbubakr Abdulgadir, Jens-Peter Kaps, Ahmad Salman. 531-536 [doi]
• A Senior-Level Analog IC Design Course built on Open-Source TechnologiesJennifer Hasler. 537-542 [doi]