Patrick Girard - researchr alias

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Viewing Publication 1 - 100 from 251

2022

2019

Modal Logic without Contraction in a Metatheory without ContractionPatrick Girard, Zach Weber. rsl, 12(4):685-701, 2019. [doi]

2018

Power-aware testing in the Era of IoTPatrick Girard. isqed 2018: 17-20 [doi]

A Special Section on Industrial Experiences in Low Power ElectronicsPatrick Girard. jolpe, 14(3):373, 2018. [doi]

A Special Section on Low Power Electronics: A Compilation of Emerging Ideas and Efficient SolutionsPatrick Girard. jolpe, 14(2):185, 2018. [doi]

2016

An effective BIST architecture for power-gating mechanisms in low-power SRAMsAlberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan. isqed 2016: 185-191 [doi]

Auto-adaptive ultra-low power ICAlberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel. dtis 2016: 1-6 [doi]

Paraconsistent dynamicsPatrick Girard, Koji Tanaka. synthese, 193(1):1-14, 2016. [doi]

Designing Functional Specifications for Complex SystemsOlga Goubali, Patrick Girard, Laurent Guittet, Alain Bignon, Djamal Kesraoui, Pascal Berruet, Jean-Frédéric Bouillon. hci 2016: 166-177 [doi]

Avoiding Inaccuracies in Task ModelsThomas Lachaume, Patrick Girard, Laurent Guittet, Allan Fousse. hci 2016: 498-509 [doi]

A hybrid power modeling approach to enhance high-level power modelsAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. ddecs 2016: 151-156 [doi]

An effective approach for functional test programs compactionAymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda. ddecs 2016: 119-124 [doi]

Design for Test and Diagnosis of Power SwitchesMiroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot. jcsc, 25(3), 2016. [doi]

A low-cost susceptibility analysis methodology to selectively harden logic circuitsImran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda. ets 2016: 1-2 [doi]

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing CoresI. Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda. et, 32(2):147-161, 2016. [doi]

2015

An ATPG Flow to Generate Crosstalk-Aware Path Delay PatternAnu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch. isvlsi 2015: 515-520 [doi]

An effective ATPG flow for Gate Delay FaultsAlberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda. dtis 2015: 1-6 [doi]

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technologySylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard. isqed 2015: 366-370 [doi]

Teaching task analysis for user interface design: lessons learned from three pilot studiesKáthia Marçal de Oliveira, Patrick Girard, Taisa Guidini Gonçalves, Sophie Lepreux, Christophe Kolski. ihm 2015: [doi]

Scan-chain intra-cell defects gradingA. Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda. dtis 2015: 1-6 [doi]

Exploring the impact of functional test programs re-used for power-aware testingA. Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda. date 2015: 1277-1280 [doi]

Design-for-Diagnosis Architecture for Power SwitchesMiroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot. ddecs 2015: 43-48 [doi]

An effective hybrid fault-tolerant architecture for pipelined coresI. Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard. ets 2015: 1-6 [doi]

Design space exploration and optimization of a Hybrid Fault-Tolerant ArchitectureI. Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda. iolts 2015: 89-94 [doi]

2014

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounceAnu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. ddecs 2014: 207-212 [doi]

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply NoiseAnu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. isvlsi 2014: 226-231 [doi]

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMsJoao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay. tvlsi, 22(11):2326-2335, 2014. [doi]

An intra-cell defect grading toolAlberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi. ddecs 2014: 298-301 [doi]

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal considerationYuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. aspdac 2014: 544-549 [doi]

Antirealism and the Conditional Fallacy: The Semantic ApproachPatrick Girard, Luca Moretti. jphil, 43(4):761-783, 2014. [doi]

Belief Revision and Dynamic LogicPatrick Girard, Hans Rott. In Alexandru Baltag, Sonja Smets, editors, Johan van Benthem on Logic and Information Dynamics. pages 203-233, Springer, 2014. [doi]

BINOS4DNA: Bitmap Indexes and NoSQL for Identifying Species with DNA Signatures through Metagenomics SamplesRamin Karimi, Ladjel Bellatreche, Patrick Girard, Ahcène Boukorca, András Hajdu. ITBAM 2014: 1-14 [doi]

Logical dynamics of belief change in the communityFenrong Liu, Jeremy Seligman, Patrick Girard. synthese, 191(11):2403-2431, 2014. [doi]

TSV aware timing analysis and diagnosis in paths with multiple TSVsCarolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. vts 2014: 1-6 [doi]

Timing-aware ATPG for critical paths with multiple TSVsCarolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. ddecs 2014: 116-121 [doi]

Intra-Cell Defects DiagnosisZhenzhou Sun, Albert Bosio, Luigi Dilillo, Patrick Girard, S. Pravossoudovich, Arnaud Virazel, Etienne Auvray. et, 30(5):541-555, 2014. [doi]

On the Generation of Diagnostic Test Set for Intra-cell DefectsZhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray. ats 2014: 312-317 [doi]

Globally Constrained Locally Optimized 3-D Power Delivery NetworksAida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel. tvlsi, 22(10):2131-2144, 2014. [doi]

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BISTAkihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang. ieicet, 97-D(10):2706-2718, 2014. [doi]

A Comprehensive Evaluation of Functional Programs for Power-Aware TestA. Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi. natw 2014: 69-72 [doi]

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and SystemsD. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich. et, 30(4):401-413, 2014. [doi]

iBoX - Jitter based Power Supply Noise sensorMiroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot. ets 2014: 1-2 [doi]

Test and diagnosis of power switchesMiroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot. ddecs 2014: 213-218 [doi]

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faultsI. Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri. ddecs 2014: 223-225 [doi]

On the Test and Mitigation of Malfunctions in Low-Power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine. et, 30(5):611-627, 2014. [doi]

2013

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power ConsumptionPaolo Bernardi, M. De Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard. jolpe, 9(2):253-263, 2013. [doi]

A novel method to mitigate TSV electromigration for 3D ICsYuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vevet, Marc Belleville. isvlsi 2013: 121-126 [doi]

Computing detection probability of delay defects in signal line tsvsC. Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Vivet, M. Belleville. ets 2013: 1-6 [doi]

Facebook and the epistemic logic of friendshipJeremy Seligman, Fenrong Liu, Patrick Girard. tark 2013: [doi]

Effect-cause intra-cell diagnosis at transistor levelZhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray. isqed 2013: 460-467 [doi]

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domainsAida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. newcas 2013: 1-4 [doi]

Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern GenerationAida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. tvlsi, 21(5):958-970, 2013. [doi]

A Study of Tapered 3-D TSVs for Power and Thermal IntegrityAida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel. tvlsi, 21(2):306-319, 2013. [doi]

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BISTA. Tomita, X. Wen, Y. Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, L.-T. Wang. ats 2013: 19-24 [doi]

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variationsGeorgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné. iolts 2013: 145-150 [doi]

Analyzing resistive-open defects in SRAM core-cell under the effect of process variabilityElena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. ets 2013: 1-6 [doi]

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM TestingElena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. ats 2013: 109-114 [doi]

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failuresElena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. dtis 2013: 39-44 [doi]

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cellElena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné. dft 2013: 143-148 [doi]

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. itc 2013: 1-10 [doi]

A built-in scheme for testing and repairing voltage regulators of low-power sramsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. vts 2013: 1-6 [doi]

Test solution for data retention faults in low-power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. date 2013: 442-447 [doi]

2012

Impact of resistive-open defects on the heat current of TAS-MRAM architecturesJ. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay. date 2012: 532-537 [doi]

Coupling-based resistive-open defects in TAS-MRAM architecturesJ. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay. ets 2012: 1 [doi]

Impact of Resistive-Bridge Defects in TAS-MRAM ArchitecturesJ. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay. ats 2012: 125-130 [doi]

Peak Power Estimation: A Case Study on CPU CoresPaolo Bernardi, M. De Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka. ats 2012: 167-172 [doi]

Advanced test methods for SRAMsAlberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. vts 2012: 300-301 [doi]

Why and How Controlling Power Consumption during Test: A SurveyAlberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel. ats 2012: 221-226 [doi]

Impact of Resistive-Bridging Defects in SRAM at Different Technology NodesRenan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. et, 28(3):317-329, 2012. [doi]

General Dynamic Dynamic LogicPatrick Girard, Jeremy Seligman, Fenrong Liu. aiml 2012: 239-260 [doi]

ProtoTask, New Task Model SimulatorThomas Lachaume, Patrick Girard, Laurent Guittet, Allan Fousse. HCSE 2012: 323-330 [doi]

Comparaison de différentes approches de simulation dans les modèles de tâchesThomas Lachaume, Sybille Caffiau, Patrick Girard, Allan Fousse, Laurent Guittet. ergoihm 2012: 57 [doi]

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and CrosstalkJunxia Ma, Mohammad Tehranipoor, Patrick Girard. et, 28(2):201-214, 2012. [doi]

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash MemoriesPierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez. et, 28(2):215-228, 2012. [doi]

Through-Silicon-Via resistive-open defect analysisC. Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. ets 2012: 1 [doi]

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault PatternsHassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen. jolpe, 8(2):248-258, 2012. [doi]

A pseudo-dynamic comparator for error detection in fault tolerant architecturesD. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich. vts 2012: 50-55 [doi]

Evaluation of test algorithms stress effect on SRAMs under neutron radiationGeorgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné. iolts 2012: 121-122 [doi]

Power Supply Noise Sensor Based on Timing Uncertainty MeasurementsMiroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot. ats 2012: 161-166 [doi]

On pinpoint capture power management in at-speed scan test generationXiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang. itc 2012: 1-10 [doi]

Defect analysis in power mode control logic of low-power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. ets 2012: 1 [doi]

Low-power SRAMs power mode control logic: Failure analysis and test solutionsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. itc 2012: 1-10 [doi]

2011

On the Modeling of Gate Delay Faults by Means of Transition Delay FaultsPaolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch. dft 2011: 226-232 [doi]

Power-Aware Test Pattern Generation for At-Speed LOS TestingAlberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, X. Wen. ats 2011: 506-510 [doi]

Vérification de cohérence entre modèles de tâches et de dialogue en conception centrée-utilisateurSybille Caffiau, Patrick Girard, Laurent Guittet, Xavier Blanc. isi, 16(5):9-41, 2011. [doi]

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron DetectorLuigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. dft 2011: 294-301 [doi]

On using address scrambling to implement defect tolerance in SRAMsRenan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. itc 2011: 1-8 [doi]

Prototypage basé sur les modèles de tâches: une étude piloteThomas Lachaume, Patrick Girard, Laurent Guittet, Allan Fousse. ihm 2011: 23 [doi]

On using a SPICE-like TSTAC™ eFlash model for design and testPierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez. ddecs 2011: 359-364 [doi]

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-FillingKohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel. ats 2011: 90-95 [doi]

Logic in the CommunityJeremy Seligman, Fenrong Liu, Patrick Girard. icla 2011: 178-188 [doi]

A study of path delay variations in the presence of uncorrelated power and ground supply noiseAida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. ddecs 2011: 189-194 [doi]

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsD. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich. ats 2011: 136-141 [doi]

Power-aware test generation with guaranteed launch safety for at-speed scan testingXiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor. vts 2011: 166-171 [doi]

Optimized march test flow for detecting memory faults in SRAM devices under bit line couplingLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. ddecs 2011: 353-358 [doi]

Failure Analysis and Test Solutions for Low-Power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine. ats 2011: 459-460 [doi]

2010

Quaternionic Spatiotemporal Filtering for Dense Motion Field Estimation in Ultrasound ImagingAdrien Marion, Patrick Girard, Didier Vray. ejasp, 2010, 2010. [doi]

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