Table of Contents

• Partial state monitoring for fault detection estimationYiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak. 1-10 [doi]
• Surviving state disruptions caused by test: A case studyKenneth P. Parker, Shuichi Kameyama, David Dubberke. 1-8 [doi]
• Logic BIST silicon debug and volume diagnosis methodologyEnamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan. 1-10 [doi]
• Development of an ATE test cell for at-speed characterization and production testingJose Moreira. 1-10 [doi]
• Evaluation of TSV and micro-bump probing for wide I/O testingKen Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel. 1-10 [doi]
• Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level currentDhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson. 1-10 [doi]
• Accurate signature driven power conscious tuning of RF systems using hierarchical performance modelsAritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee. 1-9 [doi]
• A novel Test Access Mechanism for failure diagnosis of multiple isolated identical coresManish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab. 1-9 [doi]
• State of the art low capture power methodologySwapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto. 1-10 [doi]
• Test access and the testability features of the Poulson multi-core Intel Itanium® processorDilip K. Bhavsar, Steve Poehlman. 1-8 [doi]
• Multi-site test of RF transceivers on low-cost digital ATEIvo Koren, Ben Schuffenhauer, Frank Demmerle, Frank Neugebauer, Gert Pfahl, Dirk Rautmann. 1-10 [doi]
• P-PET: Partial pseudo-exhaustive test for high defect coverageAbdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich. 1-8 [doi]
• Defect Oriented Testing for analog/mixed-signal devicesBram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Yizi Xing. 1-10 [doi]
• Optimal manufacturing flow to determine minumum operating voltageSreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas. 1-10 [doi]
• Real-time testing method for 16 Gbps 4-PAM signal interfaceMasahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu. 1-10 [doi]
• DFT for extremely low cost test of mixed signal SOCs with integrated RF and power managementRajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji. 1-10 [doi]
• Adaptive multidimensional outlier analysis for analog and mixed signal circuitsEnder Yilmaz, Sule Ozev, Kenneth M. Butler. 1-8 [doi]
• Faster-than-at-speed test for increased test quality and in-field reliabilityTomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara. 1-9 [doi]
• Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer baseChun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu. 1-10 [doi]
• Low power compression utilizing clock-gatingJanusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy. 1-8 [doi]
• Lithography aware critical area estimation and yield analysisPriyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu. 1-8 [doi]
• A fully cell-based design for timing measurement of memoryYi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao. 1-10 [doi]
• Efficient combination of trace and scan signals for post silicon validation and debugKanad Basu, Prabhat Mishra, Priyadarsan Patra. 1-8 [doi]
• Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signalHideo Okawara. 1-8 [doi]
• A novel robust and accurate spectral testing method for non-coherent samplingSiva Sudani, Minshun Wu, Degang Chen. 1-10 [doi]
• A novel scan segmentation design method for avoiding shift timing failure in scan testingYuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang. 1-8 [doi]
• Forward prediction based on wafer sort data - A case studyNik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir. 1-10 [doi]
• The gap: Test challenges in Asia manufacturing fieldXinli Gu. 1 [doi]
• Hardware hooks for transition scan characterizationPankaj Pant, Eric Skeels. 1-8 [doi]
• Multi-function multi-GHz ATE extension using state-of-the-art FPGAsA. M. Majid, David C. Keezer. 1-10 [doi]
• Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networksZhaobo Zhang, Krishnendu Chakrabarty, Zhanglei Wang, Zhiyuan Wang, Xinli Gu. 1-9 [doi]
• Generic, orthogonal and low-cost March Element based memory BISTA. J. van de Goor, Said Hamdioui, Halil Kukner. 1-10 [doi]
• Actual implementation of multi domain test: Further reduction of cost of testYasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura. 1-8 [doi]
• On using address scrambling to implement defect tolerance in SRAMsRenan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. 1-8 [doi]
• Clock-gating-aware low launch WSA test pattern generation for at-speed scan testingYi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen. 1-7 [doi]
• TM processorsLiang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson. 1-10 [doi]
• Challenges and best practices in advanced silicon debugJing Zeng. 1 [doi]
• Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scanStephen K. Sunter, Aubin Roy. 1-9 [doi]
• Design-for-debug layout adjustment for FIB probing and circuit editingKuo An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen. 1-9 [doi]
• Deterministic IDDQ diagnosis using a net activation based modelAndras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng. 1-10 [doi]
• Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case studyDragoljub Gagi Drmanac, Michael Laisne. 1-10 [doi]
• A Software-Based Self-Test methodology for on-line testing of processor cachesGeorge Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos. 1-10 [doi]
• Application of a continuous-time level crossing quantization method for timing noise measurementsTakahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu. 1-10 [doi]
• Using well/substrate bias manipulation to enhance voltage-test-based defect detectionAnne E. Gattiker, Phil Nigh. 1-6 [doi]
• IEEE Std 1581 - A standardized test access methodology for memory devicesHeiko Ehrenberg, Bob Russell. 1-9 [doi]
• EDT channel bandwidth management in SoC designs with pattern-independent test access mechanismJakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski. 1-9 [doi]
• Cell-aware analysis for small-delay effects and production test results from different fault modelsFriedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, M. Reese, J. Rearick, Jason Rivers. 1-8 [doi]
• Physically-aware analysis of systematic defects in integrated circuitsWing Chiu Tam, R. D. (Shawn) Blanton. 1-10 [doi]
• In circuit test (ICT): The king is dead; long live the king!Bailarico Balangue. 1 [doi]
• Techniques to improve memory interface test quality for complex SoCsV. R. Devanathan, Srinivas Kumar Vooka. 1-10 [doi]
• Investigation into voltage and process variation-aware manufacturing testUrban Ingelsson, Bashir M. Al-Hashimi. 1-10 [doi]
• Test cost reduction through performance prediction using virtual probeHsiu-Ming Chang, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, Kenneth M. Butler. 1-9 [doi]
• Industry leaders panel - How will testing change in the next 10 years?Phil Nigh. 1 [doi]
• Pre-bond probing of TSVs in 3D stacked ICsBrandon Noia, Krishnendu Chakrabarty. 1-10 [doi]
• Online timing variation tolerance for digital integrated circuitsGuihai Yan, Xiaowei Li 0001. 1-10 [doi]
• Analyzing ATE interconnect performance for serial links of 10 Gbps and aboveMitchell Lin, Tyler Tolman. 1-8 [doi]
• Die-level adaptive test: Real-time test reordering and eliminationKapil R. Gotkhindikar, W. Robert Daasch, Kenneth M. Butler, John M. Carulli Jr., Amit Nahar. 1-10 [doi]
• Test clock domain optimization for peak power supply noise reduction during scanJen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li. 1-8 [doi]
• End-to-end error correction and online diagnosis for on-chip networksSaeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng. 1-10 [doi]
• Power, programmability, and granularity: The challenges of ExaScale computingBill Dally. 12 [doi]
• A systems perspective on the R&D of industrial technologyJyuo-Min Shyu. 13 [doi]