Satoshi Komatsu - researchr alias

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Viewing Publication 1 - 52 from 52

2023

A PVT Variation Dependencies of VCO in Frequency Locked LoopKota Hara, Satoshi Komatsu. icecsys 2023: 1-4 [doi]

2018

A Framework for Automatic Generation of Fully Synthesizable ADPLLShinya Ubukata, Satoshi Komatsu. icecsys 2018: 57-60 [doi]

2017

A low-voltage hysteresis comparator for low power applicationsTakumi Saito, Satoshi Komatsu. icecsys 2017: 427-430 [doi]

Characteristics optimization of stochastic ADC and its automatic generation systemRyosuke Yumoto, Satoshi Komatsu. newcas 2017: 89-92 [doi]

2016

2014

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct WritingRimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. ieicet, 97-A(8):1688-1698, 2014. [doi]

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkillsMasahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada. itc 2014: 1-10 [doi]

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS ArbitersSatoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada. ieicet, 97-A(3):777-780, 2014. [doi]

A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzerJames S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada. iscas 2014: 93-96 [doi]

A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-EdgeTakahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada. ats 2014: 168-173 [doi]

2013

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projectionRimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. ispd 2013: 69-76 [doi]

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil designRimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada. aspdac 2013: 255-260 [doi]

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA CharactersRimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. ieicet, 96-A(12):2458-2466, 2013. [doi]

A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offsetJames S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada. cicc 2013: 1-4 [doi]

A novel test structure for measuring the threshold voltage variance in MOSFETsTakahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada. itc 2013: 1-8 [doi]

2012

Power integrity control of ATE for emulating power supply fluctuations on customer environmentMasahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada. itc 2012: 1-10 [doi]

A New Procedure for Measuring High-Accuracy Probability Density FunctionsTakahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira. ats 2012: 185-190 [doi]

2011

2010

An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial linksMohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada. date 2010: 1755-1760 [doi]

2009

2008

Targeting Leakage Constraints during ATPGGörschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita. ats 2008: 225-230 [doi]

VLSI Test Exercise Courses for Students in EE DepartmentSatoshi Komatsu. itc 2008: 1 [doi]

2007

2006

2005

2003

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging MethodologiesMasahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima. hicss 2003: 279 [doi]

Comparative Study On Verilog-Based And C-Based Hardware Design EducationTohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada. mse 2003: 41-42 [doi]

Irredundant address bus encoding techniques based on adaptive codebooks for low powerSatoshi Komatsu, Masahiro Fujita. aspdac 2003: 9-14 [doi]

Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive CodebooksSatoshi Komatsu, Masahiro Fujita. ieiceta, 86-A(12):3001-3008, 2003. [doi]

Engineering Changes in Field Modifiable ArchitecturesHiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita. memocode 2003: 87-94 [doi]

Verification of Synchronization in SpecC Description with the Use of Difference Decision DiagramsThanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita. ieiceta, 86-A(12):3192-3199, 2003. [doi]

2002

Field Modifiable Architecture and its Design Methodology: System Design Without Logic SynthesisYoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita. iwls 2002: 103-108

Field modifiable architecture with FPGAs and its design methodologySatoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita. fpt 2002: 382-385 [doi]

1999

Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book MethodSatoshi Komatsu, Makoto Ikeda, Kunihiro Asada. glvlsi 1999: 368-371 [doi]

1998

Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer ArchitectureSatoshi Komatsu, Makoto Ikeda, Kunihiro Asada. aspdac 1998: 323-324

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Publications by 'Satoshi Komatsu'

Viewing Publication 1 - 52 from 52

2023

2018

2017

2016

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2003

2002

1999

1998

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