Abstract is missing.
- A synchronous language at work: the story of LustreNicolas Halbwachs. 3-11 [doi]
- Synthesis of synchronous assertions with guarded atomic actionsMichael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil. 15-24 [doi]
- Automatic synthesis of cache-coherence protocol processors using BluespecNirav Dave, Man Cheuk Ng, Arvind. 25-34 [doi]
- Deterministic receptive processes are Kahn processesStephen A. Edwards, Olivier Tardieu. 37-44 [doi]
- Structural operational semantics for supporting multi-cycle operations in RTL HDLsShuqing Zhao, Daniel D. Gajski. 45-53 [doi]
- PyPBS design and methodologiesGreg Hoover, Forrest Brewer. 55-64 [doi]
- Making PVS do what you wantMyla Archer. 67 [doi]
- System design extreme makeoverDaniel Gajski. 71-75 [doi]
- Verification of parameterized hierarchical state machines using action language verifierTuba Yavuz-Kahveci, Tevfik Bultan. 79-88 [doi]
- Verification of low-level crypto-protocol implementations using automated theorem provingJan Jürjens. 89-98 [doi]
- Formal verification of SystemC by automatic hardware/software partitioningDaniel Kroening, Natasha Sharygina. 101-110 [doi]
- Translation-based co-verificationFei Xie, Xiaoyu Song, Haera Chung, Ranajoy Nandi. 111-120 [doi]
- Synchronization verification in system-level design with ILP solversThanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita. 121-130 [doi]
- Improving SystemC simulation through Petri net reductionsNicolae Savoiu, Sandeep K. Shukla, Rajesh K. Gupta. 131-140 [doi]
- Automotive software and systems engineering (Panel)Manfred Broy. 143-149 [doi]
- Service-oriented software and systems engineering - a vision for the automotive domainIngolf Krüger. 150 [doi]
- From bold idea to product - a case studyWolfgang Pree. 151 [doi]
- A formal approach to system level design: metamodels and unified design environmentsFelice Balarin, Claudio Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli. 155-163 [doi]
- Refinemant verification of fair transition systems can contribute to PLTL model checkingFrançoise Bellegarde, Samir Chouali, Jacques Julliand. 166-175 [doi]
- Three-valued logic in bounded model checkingTobias Schüle, Klaus Schneider. 177-186 [doi]
- A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machinesPanagiotis Manolios, Sudarshan K. Srinivasan. 188-197 [doi]
- On the decidability of shared memory consistency verificationAli Sezgin, Ganesh Gopalakrishnan. 199-208 [doi]
- Thunderstriking constraints with JUPITERChristos Kloukinas. 211-220 [doi]
- On the use of a high-level fault model to analyze logical consequence of propertiesStefano Brait, Franco Fummi, Graziano Pravadelli. 221-230 [doi]
- Panel on design for verificationTevfik Bultan, Constance L. Heitmeyer, John O Leary. 232-235 [doi]
- Extended abstract: on the property-based verification in SoC design flow founded on transaction level modelingNicola Bombieri, Andrea Fedeli, Franco Fummi. 239-240 [doi]
- Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTLMasahiro Fujita. 241-242 [doi]
- Extended abstract: formal verification of architectural patterns in support of dependable distributed systemsRalph D. Jeffords, Ramesh Bharadwaj. 243-244 [doi]
- Extended abstract: organizing automaton specifications to achieve faithful representationElizabeth I. Leonard, Myla Archer. 245-246 [doi]
- Extended abstract: evaluation of delay queues for a Ravenscar HW kernelGustaf Naeser, Johan Furunäs. 247-248 [doi]
- Extended abstract: requirements modeling within iterative, incremental processesLars Pareto. 249-250 [doi]
- Extended abstract: estimation times of on-chip multiprocessor stream-oriented applicationsPeter Poplavko, Twan Basten, Milan Pastrnak, Jef L. van Meerbergen, Marco Bekooij, Peter H. N. de With. 250-251 [doi]
- Extended abstract: an environment for design verification of smart card systems using attack simulation in SystemCKlaus Rothbart, Ulrich Neffe, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger. 253-254 [doi]
- Extended abstract: a race-free hardware modeling languagePatrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede. 255-256 [doi]
- Extended abstract: polynomial model-based evaluation of the branch coverage metric for functional verification of hardware systemsIñigo Ugarte, Pablo Sanchez. 257-258 [doi]
- Extended abstract: transition traversal coverage estimation for symbolic model checkingXingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya. 259-260 [doi]