Table of Contents

• Not All Xs are Bad for Scan CompressionAnshuman Chandra, Rohit Kapur. 7-12 [doi]
• Evaluation of Entropy Driven Compression Bounds on Industrial DesignsSrinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams. 13-18 [doi]
• Untestable Fault Identification in Sequential Circuits Using Model-CheckingJaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko. 21-26 [doi]
• A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length ConstraintRyoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara. 27-34 [doi]
• LIFTING: A Flexible Open-Source Fault SimulatorAlberto Bosio, Giorgio Di Natale. 35-40 [doi]
• Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCsHsiu-Ming (Sherman) Chang, Min-Sheng (Mitchell) Lin, Kwang-Ting (Tim) Cheng. 43-48 [doi]
• Low-Cost One-Port Approach for Testing Integrated RF SubstratesAbhilash Goyal, Madhavan Swaminathan. 49-54 [doi]
• Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver SystemsDeuk Lee, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee. 55-60 [doi]
• Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing OptimizationKatherine Shu-Min Li, Jr-Yang Huang. 63-68 [doi]
• Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG PatternsNitin Yogi, Vishwani D. Agrawal. 69-74 [doi]
• A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test ItselfJishun Kuang, Ouyang Xiong, Zhiqiang You. 75-80 [doi]
• XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced FaultsSunghoon Chun, YongJoon Kim, Taejin Kim, Myung-Hoon Yang, Sungho Kang. 83-88 [doi]
• A Multi-valued Algebra for Capacitance Induced Crosstalk Delay FaultsArani Sinha, Sandeep K. Gupta, Melvin A. Breuer. 89-96 [doi]
• Increasing Defect Coverage by Generating Test Vectors for Stuck-Open FaultsYoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu. 97-102 [doi]
• Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearityKoji Asami, Hidetaka Suzuki, Hiroyuki Miyajima, Tetsuya Taura, Haruo Kobayashi. 105-110 [doi]
• A Reduced Code Linearity Test Method for Pipelined A/D ConvertersJin-Fu Lin, Te-Chieh Kung, Soon-Jyh Chang. 111-116 [doi]
• Testing LCD Source Driver IC with Built-on-Scribe-Line Test CircuitryJui-Jer Huang, Chiuan-Che Li, Jiun-Lang Huang. 117-122 [doi]
• Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle PathsThomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara. 125-130 [doi]
• High Quality Pattern Generation for Delay Defects with Functional Sensitized PathsMing-Ting Hsieh, Shun-Yen Lu, Jing-Jia Liou, Augusli Kifli. 131-136 [doi]
• Refining Delay Test Methodology Using Knowledge of Asymmetric Transition DelaySean H. Wu, Sreejit Chakravarty, Alexander Tetelbaum, Li-C. Wang. 142-144 [doi]
• Effects of Advances in Analog, Mixed Signal and IO Circuits on Test StrategiesSalem Abdennadher. 145 [doi]
• Electrical Overstress Prevention & Test Best PracticesLeslie Khoo. 146 [doi]
• Low Distortion Sine Waveform Generation by an AWGAkinori Maeda. 147 [doi]
• An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based SchemeTaejin Kim, Sunghoon Chun, YongJoon Kim, Myung-Hoon Yang, Sungho Kang. 151-156 [doi]
• Optimizing Test Data Volume Using Hybrid CompressionBrion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman. 157-162 [doi]
• Cost Efficient Methods to Improve Performance of Broadcast ScanSeongmoon Wang, Wenlong Wei. 163-169 [doi]
• Hyperactive Faults Dictionary to Increase Diagnosis ThroughputChen Liu, Wu-Tung Cheng, Huaxing Tang, Sudhakar M. Reddy, Wei Zou, Manish Sharma. 173-178 [doi]
• Enhancing Transition Fault Model for Delay Defect DiagnosisWu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake. 179-184 [doi]
• Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain DiagnosisFei Wang, Yu Hu, Yu Huang 0005, Jing Ye, Xiaowei Li 0001. 190-192 [doi]
• The HiZ Problem of Power Management IC TestingHagen Goller. 193 [doi]
• Total Jitter Measurement for Testing HSIO Integrated SoCsTakahiro J. Yamaguchi, Masahiro Ishida. 194 [doi]
• Load-Board/PCB Noise Suppression via Electromagnetic Band Gap Power Plane PatterningFidel Muradali, Suzanne Huh, Madhavan Swaminathan. 195 [doi]
• Defect Detection Rate through IDDQ for Production TestingJunichi Hirase. 199-205 [doi]
• Variation Aware Analysis of Bridging Fault TestingUrban Ingelsson, Bashir M. Al-Hashimi, Peter Harrod. 206-211 [doi]
• Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic DefectsDongok Kim, Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman. 217-220 [doi]
• How To Increase the Effectiveness of Yield Diagnostics-Is DFM the Answer to This?Anis Uzzaman. 221 [doi]
• Targeting Leakage Constraints during ATPGGörschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita. 225-230 [doi]
• Power Management for Wafer-Level Test During Burn-InSudarshan Bahukudumbi, Krishnendu Chakrabarty. 231-236 [doi]
• Test Generation for State Retention LogicKrishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor. 237-242 [doi]
• Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design TechniquesChun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu. 245-250 [doi]
• On-Chip Test Generation Mechanism for Scan-Based Two-Pattern TestsNan-Cheng Lai, Sying-Jyan Wang. 251-256 [doi]
• Level-Testability of Multi-operand AddersNobutaka Kito, Naofumi Takagi. 260-262 [doi]
• System Level LBIST ImplementationFei Zhuang, Junbo Jia, Xiangfeng Li. 263 [doi]
• CooLBIST: An Effective Approach of Test Power Reduction for LBISTJun Matsushima, Yoichi Maeda, Masahiro Takakura. 264 [doi]
• Practical Challenges in Logic BIST ImplementationShianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami. 265 [doi]
• USB2.0 Logic Built In Self Test MethodologyKeanhong Boey, Kok Sing Yap, Wai Mun Ng. 266 [doi]
• Shared At-Speed BIST for Parallel Test of SRAMs with Different Address SizesTomonori Sasaki, Yoshiyuki Nakamura, Toshiharu Asaka. 267 [doi]
• Experimental Results of Built-In Jitter Measurement for Gigahertz ClockNai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen. 268 [doi]
• Leading Edge Technology and Test NoiseKatayama Takayuki, Kou Ebihara, Goro Imaizumi. 269 [doi]
• DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog CircuitsRicky Smith, Jiang Shi. 270 [doi]
• Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug MethodKhairul Khusyari, Wei Tee Ng, Neal Jaarsma, Robert Abraham, Peng Weng Ng, Boon Hui Ang, Chin Hu Ong. 271 [doi]
• Detectability of the Two-Dimensional Detector for Time Resolved Emission MeasurementNobuyuki Hirai. 272 [doi]
• Protocol Aware Test Methodologies Using TodayShawn Molavi, Andy Evans, Ray Clancy. 273 [doi]
• Core-Level Compression Technique Selection and SOC Test Architecture DesignAnders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty. 277-282 [doi]
• Simulation-Driven Thermal-Safe Test Time Minimization for System-on-ChipZhiyuan He, Zebo Peng, Petru Eles. 283-288 [doi]
• A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoCHyunbean Yi, Sungju Park, Sandip Kundu. 289-294 [doi]
• Accelerated Functional Testing of Digital Microfluidic BiochipsDebasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Bhargab B. Bhattacharya, D. Dutta Majumder, Krishnendu Chakrabarty. 295-300 [doi]
• On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon ValidationXiao Liu, Qiang Xu. 303-308 [doi]
• A Robust Automated Scan Pattern Mismatch DebuggerKun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng. 309-314 [doi]
• An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level DesignsYoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita. 315-320 [doi]
• Coverage Directed Test Generation: Godson ExperienceHaihua Shen, Wenli Wei, Yunji Chen, Bowen Chen, Qi Guo. 321-326 [doi]
• Test Power Reduction by Blocking Scan Cell OutputsXijiang Lin, Janusz Rajski. 329-336 [doi]
• Two-Gear Low-Power Scan TestChao-Wen Tzeng, Shi-Yu Huang. 337-342 [doi]
• DCScan: A Power-Aware Scan Testing ArchitectureGui Dai, Zhiqiang You, Jishun Kuang, Jiedi Huang. 348-455 [doi]
• A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore ChipsYu-Jen Huang, Jin-Fu Li. 357-362 [doi]
• A Software-Based Test Methodology for Direct-Mapped Data CacheYi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen. 363-368 [doi]
• Time-Multiplexed Online Checking: A Feasibility StudyMing Gao, Hsiu-Ming (Sherman) Chang, Peter Lisherness, Kwang-Ting (Tim) Cheng. 371-376 [doi]
• On-Line Instruction-Checking in Pipelined MicroprocessorsStefano Di Carlo, Giorgio Di Natale, Riccardo Mariani. 377-382 [doi]
• Design of FSM with Concurrent Error Detection Based on Viterbi DecodingMing Li, Shiyi Xu, Enjun Xia, Fayu Wang. 383-388 [doi]
• PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression EnvironmentYi-Tsung Lin, Meng-Fan Wu, Jiun-Lang Huang. 391-396 [doi]
• CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan TestingHiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mark Tehranipoor. 397-402 [doi]
• Power Analysis and Reduction Techniques for Transition Fault TestingKhushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill. 403-408 [doi]
• Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-CellsStefano Di Carlo, Alessandro Savino, Alberto Scionti, Paolo Prinetto. 411-416 [doi]
• Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance FaultWan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, Cheng-Wen Wu. 417-422 [doi]
• GDDR5 TrainingHubert Werkmann, Dong Myong Kim, Shinji Fujita. 423-428 [doi]
• A Re-design Technique for Datapath Modules in Error Tolerant ApplicationsDoochul Shin, Sandeep K. Gupta. 431-437 [doi]
• Reliable Network-on-Chip Router for Crosstalk and Soft Error ToleranceYing Zhang, Huawei Li, Xiaowei Li 0001. 438-443 [doi]
• Analyses on Trend of Accidents in Financial Information Systems Reported by Newspapers from the Viewpoint of DependabilityKoichi Bando, Kenji Tanaka. 444-450 [doi]