Shianling Wu - researchr alias

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Viewing Publication 1 - 23 from 23

2012

2011

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock DomainsShianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu. tcad, 30(3):455-463, 2011. [doi]

2010

2009

2008

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPGLaung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu. dt, 25(2):122-130, 2008. [doi]

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 StandardLaung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li. itc 2008: 1-9 [doi]

Practical Challenges in Logic BIST ImplementationShianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami. ats 2008: 265 [doi]

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan DesignsShianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte. dft 2008: 143-151 [doi]

2006

A Novel and Practical Control Scheme for Inter-Clock At-Speed TestingHiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu. itc 2006: 1-10 [doi]

2005

2004

VirtualScan: A New Compressed Scan Technology for Test Cost ReductionLaung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai. itc 2003: 916-925 [doi]

2000

Collaboration between Industry and Academia in Test ResearchKwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu. ats 2000: 17 [doi]

1998

A non-enumerative path delay fault simulator for sequential circuitsCarlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu. itc 1998: 934-943 [doi]

1996

Lessons Learned from Practical Applications of BIST/B-S TechnologyNajmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau. ats 1996: 251-257 [doi]

1985

A Sequential Circuit Test Generation SystemSivanarayana Mallela, Shianling Wu. itc 1985: 57-61

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