Abstract is missing.
- Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and AgingKunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe. 3 [doi]
- An Analytical Error Model for Pattern Clipping in DNA Self-AssemblyZahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi. 7-15 [doi]
- Logic Gate Failure Characterization for Nanoelectronic EDA ToolsPayman Zarkesh-Ha, Ali Arabi M. Shahi. 16-23 [doi]
- Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated ExplorationPritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz. 24-31 [doi]
- Reliability-Driven System-Level Synthesis of Embedded SystemsCristiana Bolchini, Antonio Miele. 35-43 [doi]
- Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space ApplicationsSalvatore Campagna, Moazzam Hussain, Massimo Violante. 44-51 [doi]
- A Hardware-Oriented Fault-Tolerant Routing Algorithm for Irregular 2D-Mesh Network-on-Chip without Virtual ChannelsYusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi, Takeshi Hattori. 52-59 [doi]
- Minimal Path, Fault Tolerant, QoS Aware Routing with Node and Link Failure in 2-D Mesh NoCNavaneeth Rameshan, Vijay Laxmi, Manoj Singh Gaur, Mushtaq Ahmed, Krishan Kumar Paliwal. 60-66 [doi]
- Circuit Failure Prediction by Field Test - A New Task of TestingYasuo Sato. 69-70 [doi]
- Soft Error Tolerant BILBO FFKazuteru Namba, Hideo Ito. 73-81 [doi]
- A Design of Self-Defect-Compensatable Hardware Neuron for Multi-layer Neural NetworksKunihito Yamamori, Keisuke Tashiro, Masamichi Kusano, Ikuo Yoshihara. 82-89 [doi]
- Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data PathsMario Schölzel, Sebastian Müller. 90-98 [doi]
- The Impact of Manufacturing Defects on the Fault Tolerance of TMR-SystemsMarc Hunger, Sybille Hellebrand. 101-108 [doi]
- CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and AnalysisTomoyuki Nagase, Kenji Ichijo, Akiko Narita, Yoshio Yoshioka. 109-114 [doi]
- Programmable MBIST Merging FSM and Microcode Techniques Using Macro CommandsNurQamarina MohdNoor, Azilah Saparon, Yusrina Yusof. 115-121 [doi]
- A Strategy for Interconnect Testing in Stacked Mesh Network-on-ChipMin-Ju Chan, Chun-Lung Hsu. 122-128 [doi]
- Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in MemoryMing Zhu, Liyi Xiao, Shuhao Li, Yanjing Zhang. 129-135 [doi]
- Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing ApplicationsChun-Lung Hsu, Chen-Wei Lan, Yu-Chih Lo, Yu-Sheng Huang. 136-143 [doi]
- High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic MemoriesNor Zaidi Haron, Said Hamdioui. 144-151 [doi]
- A Probabilistic Method to Detect Anomalies in Embedded SystemsMahroo Zandrahimi, Alireza Zarei, Hamid R. Zarandi. 152-159 [doi]
- Duplication Based One-to-Many Coding for Trojan HW DetectionOsnat Keren, Ilya Levin, Mark G. Karpovsky. 160-166 [doi]
- SEU-Hardened Dual Data Rate Flip-Flop Using C-ElementsSrikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth. 167-171 [doi]
- Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development SystemTatsuya Suto, Kenji Ichijo, Yoshio Yoshioka. 172-179 [doi]
- Case Studies on Transition Fault Test Generation for At-speed Scan TestingNor Azura Zakaria, Edward V. Bautista Jr., Suhaimi Bahisham Jusoh, Weng Fook Lee, Xiaoqing Wen. 180-188 [doi]
- A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA PlatformsCristiana Bolchini, Luca Fossati, David Merodio Codinachs, Antonio Miele, Chiara Sandionigi. 191-199 [doi]
- A New Soft-Error Resilient Voltage-Mode Quaternary LatchEduardo Luis Rhod, Luca Sterpone, Luigi Carro. 200-208 [doi]
- An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential CircuitsDan Zhu, Tun Li, Sikun Li. 209-217 [doi]
- A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAsHassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi. 218-224 [doi]
- Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-ClouseauTakashi Aikyo. 227 [doi]
- Tradeoffs in Imager Design with Respect to Pixel Defect RatesGlenn H. Chapman, Jenny Leung, Israel Koren, Zahava Koren. 231-239 [doi]
- Time/Temperature Degradation of Solar Cells under the Single Diode ModelPilin Junsangsri, Fabrizio Lombardi. 240-248 [doi]
- Modeling Open Defects in Nanometric Scale CMOSAnant Narayan Hariharan, Salvatore Pontarelli, Marco Ottavi, Fabrizio Lombardi. 249-257 [doi]
- Low-Power Testing for Low-Power DevicesXiaoqing Wen. 261 [doi]
- On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock JitterMartin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman. 265-272 [doi]
- Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and PerformancePriyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz. 273-279 [doi]
- Single Event Induced Double Node Upset Tolerant LatchKazuteru Namba, Masatoshi Sakata, Hideo Ito. 280-288 [doi]
- Modelling a CNTFET with Undeposited CNT DefectsGeunho Cho, Fabrizio Lombardi, Yong-Bin Kim. 289-296 [doi]
- Industrial Approach for DependabilityNobuyasu Kanekawa. 299 [doi]
- A Multi-dimensional Iddq Testing Method Using Mahalanobis DistanceYoshiyuki Nakamura, Masashi Tanaka. 303-309 [doi]
- Test Selection Policies for Faster Incremental Fault DetectionLuca Amati, Cristiana Bolchini, Fabio Salice. 310-318 [doi]
- Massively Deployable Intelligent Sensors for the Smart Power GridVijay K. Jain, Glenn H. Chapman. 319-327 [doi]
- Hybrid Built-In Self-Test Architecture for Multi-port Static RAMsLizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen. 331-339 [doi]
- AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay DefectsTsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang. 340-348 [doi]
- Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault PairsIrith Pomeranz, Sudhakar M. Reddy. 349-357 [doi]
- Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock DomainsShianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang. 358-366 [doi]
- A Study of eSRAM TestabilityNoriaki Takagi. 369 [doi]
- Prolongation of Lifetime and the Evaluation Method of Dependable SSDKensuke Tai, Masato Kitakami. 373-381 [doi]
- Warning Prediction Sequential for Transient Error PreventionBishnu Prasad Das, Hidetoshi Onodera. 382-390 [doi]
- Transient Fault and Soft Error On-die Monitoring SchemeDaniele Rossi, Martin Omaña, Cecilia Metra. 391-398 [doi]
- A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite FieldsBijan Ansari, Ingrid Verbauwhede. 399-407 [doi]
- Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate ArraysDaisaku Seto, Minoru Watanabe. 411-419 [doi]
- Error Detection and Correction in Content Addressable MemoriesSalvatore Pontarelli, Marco Ottavi, Adelio Salsano. 420-428 [doi]
- Online Multiple Fault Detection in Reversible CircuitsNavid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori. 429-437 [doi]
- Analog Design for a Power Transmission Line Sensing and Analysis VLSI ChipErik MacLean, Vijay K. Jain. 438-446 [doi]