Table of Contents

• Experiences and Expectations in VLSI TestingEdward B. Eichelberger. 4
• The Growth of Application Specific Integrated Circuits: Opportunities and ChallengesPaul M. Russo. 5
• Easing the Transition from Design to TestThomas M. McWilliams. 6
• Complexity, Test, and the Productivity Challenge of the 90sJohn Manzo. 7-9
• Parallel Programming Significantly Improves Production NVM Wafer SortJohn Stone, Howard Ignatius, Randall Nuss. 10-18
• Power Conditioning Provides Documented Productivity Gains in Semiconductor Fabrication and ATEPeter Nystrom, Steven Cosgrove. 19-22
• Financial Implications of a Detailed Analysis of Test Floor OperationsJudith E. Dayhoff, Robert W. Atherton. 23-32
• Low Cost Test System Speeds Design Verification for Custom VLSIKen Lindsay. 33-39
• Automatic Test Generation for Generic Scan DesignsMatthew Adiletta, Elizabeth M. Cooper, Keith Gutfreund. 40-44
• Test Generation In Lamp2: System OverviewMiron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller. 45-48
• Test Generation In Lamp2: Concepts and AlgorithmsMiron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller. 49-56
• A Sequential Circuit Test Generation SystemSivanarayana Mallela, Shianling Wu. 57-61
• A Method for Test Generation Directly from Testability AnalysisAngelo C. Hung, Francis C. Wang. 62-78
• Guided Inconsistent Path Sensitization: Method And Experimental ResultsErwin Trischler. 79-87
• Concatenable Polydividers : Bit-Sliced LFSR Chips for Board Self-TestDilip K. Bhavsar. 88-93
• Test Length for Pseudo Random TestingCary K. Chin, Edward J. McCluskey. 94-99
• Random Pattern Testing for Data-Line Faults in an Embedded Multiport MemoryJacob Savir, William H. McAnney, Salvatore R. Vecchio. 100-105
• Random Pattern Testing for Address-Line Faults in an Embedded Multiport MemoryJacob Savir, William H. McAnney, Salvatore R. Vecchio. 106-114
• Built-In Self Test Input Generator for Programmable Logic ArraysJohn Salick, Bill Underwood, M. Ray Mercer. 115-125
• Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open FaultsGary L. Craig, Charles R. Kime. 126-139
• A Computer System Diagnostic Strategy Based on ROM-Resident DiagnosticsSherri Klosterman. 140-144
• Concurrent System-Level Error Detection Using a Watchdog ProcessorAamer Mahmood, Edward J. McCluskey, Aydin Ersoz. 145-152
• Semiconductor Test Equipment Viewed as an Auto-Alignment SystemDavid S. Curry. 153-158
• The Uses and Costs of the Addition of Remote Operation Capability to New ProductsDonald H. Lenhert. 159-168
• A Fast, Probabilistic Algorithm for Functional Testing of Random Access Memory SystemsDavid M. Jacobson. 169-179
• RF Calibration in ATE SystemsWilliam Corley, David S. Curry. 180-184
• Calibration of Systematic Errors in Precision Time-Interval CountersDavid C. Chu. 185-190
• A Method of Reducing ATE System Error Components and Guaranteeing Subnanosecond Measurement AccuraciesJim Healy, Gary Ure. 191-202
• Achieving Accurate Timing Measurements on TTL/CMOS Devices in a Manufacturing/Incoming Inspection EnvironmentDennis Petrich. 203-219
• Timing Accuracy Measurement SystemGarry C. Gillette. 220-223
• Training Tomorrow s Test Engineers: Experiences in Teaching an Undergraduate Course in VLSI TestingRobert J. Feugate Jr., Steven M. McIntyre. 224-229
• Future Trends in Test of Electronic Circuits With Implications tor Entry Level Test ProfessionalsAlbert B. Grubbs Jr., Glenn Neland. 230-234
• Test TeachingEdward J. McCluskey. 235
• What Do You Say When Writing a Text About Test ?Alexander Miczo. 236-238
• Test Technology In a University SettingKenneth Rose. 239-240
• Curriculum for a Rapidly Changing TechnologyAl A. Tuszynski. 241-243
• Enhancing Device Test Programming Productivity: The CATalyst Automated Test Program GeneratorJames G. Wilber. 252-262
• Language Independent Test GenerationKeiji Muranaga, Kyoshiro Sakurada, Yukio Oikawa. 263-270
• DIP : A Diagnostics ProcessorShmuel Shalem. 271-278
• The Autopal Test ProcessMaurizio Contini. 279-285
• Simplifying Analog Device Test Program GenerationClaude J. Pany. 286-290
• Recycling Functional Test Vectors: Techniques and Tools for Pattern ConversionTom Middleton. 291-303
• An Algorithm to Generate Tests for MOS Circuits at the Switch LevelHarry H. Chen, Robert G. Mathews, John A. Newkirk. 304-312
• Defect Analysis and Fault Modeling in MOS TechnologyR. Chandramouli, Hector R. Sucar. 313-321
• Testing CMOS VLSI: Tools, Concepts, and Experimental ResultsMark E. Turner, Duane G. Leet, Ronald J. Prilik, David J. McLean. 322-328
• An AC/DC Test Generation System for Gate Array LSIsT. Shimono, K. Oozeki, M. Takahashi, Masato Kawai, S. Funatsu. 329-333
• The Error Latency of Delay Faults in Combinational and Sequential CircuitsKenneth D. Wagner. 334-341
• Model for Delay Faults Based upon PathsGordon L. Smith. 342-351
• Self-Test of Random Access MemoriesPaul H. Bardell, William H. McAnney. 352-355
• Self-Test for MicroprocessorsRobert H. Fujii, Jacob A. Abraham. 356-361
• Automatic Design of Exhaustively Self-Testing Chips with Bilbo ModulesAndrzej Krasniewski, Alexander Albicki. 362-371
• Isolating Failures within VLSI Chips That Incorporate Signature Analysis and Set/Scan TechniquesFrances D. Koo, Gene W. Lee. 372-379
• Systematic and Structured Methods for Digital Board TestingFrans P. M. Beenker. 380-385
• Automating Test-Bed Fault Detection and DiagnosisStephen F. Filippone. 386-392
• A Programmable Bus Emulation Technique for Processor Based and Peripheral Printed Circuit BoardsJaffery C. Phillips. 393-398
• Automatic Visual Test of Surface Mount AssembliesDom Marro. 399-402
• Flexible Inspection Systems (FIS) for Printed Circuit Board Production: ATE Finds a Quality PartnerScott T. Jones. 403-412
• New Concepts of Applying Thermographic Testing to Printed Circuit Boards and Finished ProductsHerb Boulton. 413-419
• MHz Frequency Counting with VLSI Testers 420Antony K. Stevens. 420-427
• Universal Signal Routing CardD. R. Morris. 428-430
• Custom VLSI Test SystemRyozou Yoshino, Ryuichi Takagi. 431-437
• Memory Embedded VLSI Gate Array TestingM. Shimizu, N. Okino, J. Nishiura, H. Maruyama. 438-444
• Asynchronous FIFO s Require Special AttentionD. Rodgers, M. Shepherd. 445-450
• Test Pattern Considerations for Fault Tolerant High Density DRAMHiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano. 451-455
• Considerations of the Testing of RAMs with Dual PortsT. Fujieda, N. Arai. 456-461
• A New Parallel Test Approach for Large MemoriesT. Sridhar. 462-470
• A Methodology for Testing Content Addressable MemoriesGrady Giles, Craig Hunter. 471-475
• An Operationally Efficient Scheme for Exhaustive Test-Pattern Generation Using Linear CodesNagesh Vasanthavada, Peter N. Marinos. 476-482
• Functional Test Generation for LSI Circuits Described by Binary Decision DiagramsMagdy S. Abadir, Hassan K. Reghbati. 483-492
• Multiple-Fault Detection in Iterative Logic ArraysWu-Tung Cheng, Janak H. Patel. 493-499
• Testing Properties and Applications of Inverter-Free PLA sVinod K. Agarwal, Janusz Rajski. 500-507
• Efficient Test Generation AlgorithmsAndrew V. Goldberg, Karl J. Lieberherr. 508-517
• The Effects of Backdriving Integrated Circuits : An Accurate Electro-Thermal ModelJill M. McPhee. 518-522
• Backdrive Stress-Testing of CMOS Gate Array CircuitsFrank H. Hielscher, John C. Pagano. 523-533
• Overdriving NMOS and CMOS VLSI CircuitsJosef H. Hendriks. 534-539
• Various Architectures of Systems for Measuring Early-Life Failure Rates of Semiconductor ComponentsHoward D. Helms. 540-543
• Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICsJerry M. Soden, Charles F. Hawkins. 544-557
• Automated Design for Testability of Semicustom Integrated CircuitsPatrick P. Fasang, Michael A. Schuette, John Paul Shen, William A. Gwaltney. 558-564
• Programmable Logic: Testability by DesignRobert J. Orsello. 565-566
• On the Design of Testable Domino PLAsDong Sam Ha, Sudhakar M. Reddy. 567-573
• A Testable Design of Programmable Logic Arrays with Universal Control and Minimal OverheadHideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita. 574-582
• : A Testable PLA Design with Minimal Hardware and Test SetJames Jacob, Nripendra N. Biswas. 583-588
• Design of a Class of Self-Exercising Combinational CircuitsAlbert Lam, Savio N. Chau, Huy Luong. 589-601
• Algorithms for High-Performance Fixture WiringMartin I. Eiger, Michele J. Chabot. 602-609
• A Computerized Solution to the Fixture-Wiring ProblemH. S. Lahman, C. L. Johnson. 610-617
• Auto-Probing on the L200 Functional TesterTim Moore, Stephen Garner. 618-628
• Driver/Sensor Design for High-Performance ATEJames Congdon. 629-633
• An On-Lined Laser Probing System for Diagnosing Scaled VLSIT. Shiragasawa, M. Sugano, Yoshihisa Mano, M. Noyori. 634-642
• Automated Fault Diagnostic EB Tester and Its Application to a 40K-Gate VLSI CircuitNorio Kuji, Teruo Tamama. 643-651
• A Comprehensive Approach to Test Program Debugging for High Performance VLSI Test SystemsS. Daniel Lee, Lisa Deerr Li. 652-665
• Integrated Test Program Development PackageBrijendra Sharma, Colin McIntyre, Gerard Labonville, Jose Avila. 666-671
• Waveform: A Software Tool for Efficient Test Program DevelopmentArthur E. Downey. 672-677
• TRS and DTS : IC Test Result StandardsReed I. White. 678-684
• Tester Independent Support Software System (TISSS)L. J. Falkenstrom, David C. Keezer, A. Patterson, Robert M. Rolfe, J. Wolcott. 685-691
• Maintaining Simulation Accuracy through Physical Device ModelsDavid Giles, Kenneth R. Bowden, Mike Haney, Gregory A. Maston. 692-695
• The Modern Fault DictionaryJeremy Richman, Kenneth R. Bowden. 696-702
• Concurrent Simulation at the Switch, Gate, and Register LevelsErnst Ulrich. 703-709
• CHIEFS : A Concurrent, Hierarchical and Extensible Fault SimulatorWilliam A. Rogers, Jacob A. Abraham. 710-716
• AFS : An Approximate Fault SimulatorMasahiko Kawamura, Kanji Hirabayashi. 717-721
• Accurate Fault Modeling and Efficient Simulation of Differential CVS CircuitsZeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman. 722-731
• Faults in Microprogrammed and Hardwired ControlYashwant K. Malaiya. 732
• Evaluation ot Monitor Complexity for Concurrently Testing Microprogrammed Control UnitsCarl Staelin, Alexander Albicki. 733-736
• A Microprocessor Test Approach Allowing Fault LocalizationRaoul Velazco, Haissam Ziade, E. Kolokithas. 737-743
• Testability Features of the MC68HC11D. K. Verbeek, W. C. Bruce. 744-751
• Test Features ot the MC68881 Floating-Point CoprocessorLuis A. Basto, John R. Kuban. 752-759
• Testability Analysis of Programmable Array LogicPredrag G. Kovijanic, Ramesh G. Kulkarni. 760-768
• A New Approach to the Use of Testability Analysis in Test GenerationBalakrishnan Krishnamurthy, Richard Li-Cheng Sheng. 769-778
• A Statistical Calculation of Fault Detection Probabilities By Fast Fault SimulationJohn A. Waicukauski, Eric Lindbloom, Edward B. Eichelberger, Donato O. Forlenza, Tim McCarthy. 779-784
• A Fast Fault Grader: Analysis and ApplicationsFranc Brglez. 785-794
• Low-Cost Fault Simulation: Why, When and HowMiron Abramovici. 795
• STAFAN Takes a Middle CourseVishwani D. Agrawal. 796
• Fault Coverage Tools: Case StudiesFranc Brglez. 797-800
• Statistical Fault Sampling and Full Fault SimulationPrabhakar Goel, Chi-Lai Huang. 801-802
• Predicting Fault Coverage from Probabilistic TestabilitySharad C. Seth. 803-807
• Statistical Failure Detection Methods for Linear Analog SystemsD. Kazakos. 808-812
• : Modeling and Test Point Selection for Data Converter TestingGerard N. Stenbakken, T. Michael Souders. 813-817
• Testing A/D Converters on MicrocomputersClyde Browning. 818-824
• DSP Synthesized Signal Source for Analog Testing Stimulus and New Test MethodH. Kitayoshi, S. Sumida, K. Shirakawa, S. Takeshita. 825-834
• Employing Multiple Test Techniques for Complex Telecommunications DevicesBrent Schusheim. 835-841
• Test of Digital Transversal FiltersF. Matthiesen, Michael J. Ohletz. 842-847
• Knowledge Acquisition for ATE DiagnosisPatricia M. Ryan, A. Jesse Wilkinson. 848-856
• The Design and Construction of a Rule Base and an Inference Engine for Test System DiagnosisOliver Grillmeyer, A. Jesse Wilkinson. 857-867
• An Expert System for In-Circuit Fault DiagnosisLarry Apfelbaum. 868-874
• Detectable CMOS Faults in Switch-Level SimulationStephen L. Lusky, T. Sridhar. 875-883
• Rule Based Testability Checker and Test GeneratorKyushik Son. 884-891
• The Cost and Speed Barriers in LSI/VLSI Testing : Can They Be Overcome By Testability Design ?Frank F. Tsui. 892-906
• Multiple Output Pass Networks: Design and TestingAli Feizi, Damu Radhakrishnan. 907-911
• The Challenge of Configurable Logic Array TestingBell Liu. 912-921
• VLSI Functional Test Pattern Generation: A Design and ImplementationTonysheng Lin, Stephen Y. H. Su. 922-929
• Contactless VLSI Laser ProbingUming Ko, Dinesh G. Patel, Francois J. Henley. 930-937
• Microprocessor Speed Optimization Using Pattern-Recognition Analysis of Parametric Test DataRobert W. Atherton, John L. Mudge. 938-948
• Reducing Test Program Development Time for Memory DevicesJohn D. Tobey. 949-953
• Case Study: ATE Networking Using Peripheral EmulationWilliam P. Allaire. 954-961
• Linking Design Tools to In-Circuit Test SystemsMichael Dapron. 962-971
• Converting Device Test Vectors to an In-Circuit Board Test EnvironmentPeter Hansen. 972-979
• Distributed Factory Data Management-Breaking the Network BottleneckSteven R. Nelson. 980-986