Franc Brglez - researchr alias

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Viewing Publication 1 - 63 from 63

2017

Low-autocorrelation binary sequences: On improved merit factors and runtime predictions to achieve themBorko Boskovic, Franc Brglez, Janez Brest. asc, 56:262-285, 2017. [doi]

On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walksFranc Brglez, Borko Boskovic, Janez Brest. cec 2017: 1000-1007 [doi]

2007

Performance testing of combinatorial solvers with isomorph class instancesFranc Brglez, Jason A. Osborne. expcs 2007: 13 [doi]

High-contrast algorithm behavior: observation, hypothesis, and experimental designMatthias F. M. Stallmann, Franc Brglez. expcs 2007: 12 [doi]

2005

On SAT instance classes and a method for reliable performance experiments with SAT solversFranc Brglez, Xiao Yu Li, Matthias F. M. Stallmann. AMAI, 43(1):1-34, 2005. [doi]

Effective bounding techniques for solving unate and binate covering problemsXiao Yu Li, Matthias F. M. Stallmann, Franc Brglez. dac 2005: 385-390 [doi]

2003

A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit PropagationXiao Yu Li, Matthias F. M. Stallmann, Franc Brglez. sat 2004: 53-68 [doi]

2001

A Universal Client for Distributed Networked Design and ComputingFranc Brglez, Hemang Lavana. dac 2001: 401-406 [doi]

Design of experiments and evaluation of BDD ordering heuristicsJustin E. Harlow III, Franc Brglez. STTT, 3(2):193-206, 2001. [doi]

Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing MinimizationMatthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh. jea, 6:8, 2001.

2000

The Scientific Method and Design and TestFranc Brglez. dt, 17(3):142-144, 2000. [doi]

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the InternetHemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha Chandrakasan. iccd 2000: 567-570 [doi]

1999

Design of experiments in CAD: context and new data sets for ISCAS 99Franc Brglez, Rolf Drechsler. iscas 1999: 424-427 [doi]

Equivalence classes of circuit mutants for experimental designDebabrata Ghosh, Franc Brglez. iscas 1999: 432-435 [doi]

Mirror, mirror, on the wall...is the new release any different at all? [BDDs]Justin E. Harlow III, Franc Brglez. iscas 1999: 452-455 [doi]

User-configurable experimental design flows on the web: the ISCAS 99 experimentsHemang Lavana, Franc Brglez, Robert B. Reese. iscas 1999: 440-443 [doi]

Heuristics and Experimental Design for Bigraph Crossing Number MinimizationMatthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh. alenex 1999: 74-93 [doi]

Evaluating iterative improvement heuristics for bigraph crossing minimizationMatthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh. iscas 1999: 444-447 [doi]

1998

1997

Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributionsNevin Kapur, Debabrata Ghosh, Franc Brglez. ispd 1997: 136-143 [doi]

Internet-based workflows: a paradigm for dynamically reconfigurable desktop environmentsHemang Lavana, Amit Khetawat, Franc Brglez. group 1997: 204-213 [doi]

Executable Workflows: A Paradigm for Collaborative Design on the InternetHemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski. dac 1997: 553-558 [doi]

1996

Fast true delay estimation during high level synthesisSubhrajit Bhattacharya, Sujit Dey, Franc Brglez. tcad, 15(9):1088-1105, 1996. [doi]

1995

Partial scan selection for user-specified fault coverageClay Gloster, Franc Brglez. eurodac 1995: 111-116 [doi]

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlistsRoman Kuznar, Franc Brglez. iccad 1995: 644-649 [doi]

Detectable perturbations: a paradigm for technology-specific multi-fault test generationAndrej Zemva, Franc Brglez. vts 1995: 350-357 [doi]

1994

Report of the 1993 workshop on rapid prototyping of microelectronic systems for universitiesPhil Allen, Franc Brglez, Hal Carter, Robert Caverly, Jerry Dillion, Albert Lo, Ron Lomax, John Oldfield, Cesar Pina, T. J. Wilkinson. sigarch, 22(3):19-26, 1994. [doi]

Provably correct high-level timing analysis without path sensitizationSubhrajit Bhattacharya, Sujit Dey, Franc Brglez. iccad 1994: 736-742 [doi]

Clock Period Optimization During Resource Sharing and AssignmentSubhrajit Bhattacharya, Sujit Dey, Franc Brglez. dac 1994: 195-200 [doi]

Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive SpecificationsSubhrajit Bhattacharya, Sujit Dey, Franc Brglez. dac 1994: 491-496 [doi]

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitionsRoman Kuznar, Baldomir Zajc, Franc Brglez. eurodac 1994: 271-276 [doi]

Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and InterconnectRoman Kuznar, Franc Brglez, Baldomir Zajc. dac 1994: 238-243 [doi]

Introduction of Permissible Bridges with Application to Logic Optimization after Technology MappingBernhard Rohfleisch, Franc Brglez. eurodac 1994: 87-93

A Functionality Fault Model: Feasibility and ApplicationsAndrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc. eurodac 1994: 152-158

1993

Transformations and resynthesis for testability of RT-level control-data path specificationsSubhrajit Bhattacharya, Franc Brglez, Sujit Dey. tvlsi, 1(3):304-318, 1993. [doi]

A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema?Franc Brglez. dt, 10(3):87-91, 1993.

Cost Minimization of Partitions into Multiple DevicesRoman Kuznar, Franc Brglez, Krzysztof Kozminski. dac 1993: 315-320 [doi]

1992

1991

Identification and Resynthesis of Pipelines in Sequential NetworksSujit Dey, Franc Brglez, Gershon Kedem. vlsi 1992: 439-449

Partitioning Sequential Circuits for Logic OptimizationSujit Dey, Franc Brglez, Gershon Kedem. iccd 1991: 70-76

1990

Built-in self-test with weighted random pattern hardwareFranc Brglez, Clay S. Gloster Jr., Gershon Kedem. iccd 1990: 161-166 [doi]

Corolla Based Circuit Partitioning and ResynthesisSujit Dey, Franc Brglez, Gershon Kedem. dac 1990: 607-612 [doi]

OASIS: a silicon compiler for semi-custom designGershon Kedem, Franc Brglez, Krzysztof Kozminski. rsp 1990: 75 [doi]

1989

Hardware-Based Weighted Random Pattern Generation for Boundary ScanFranc Brglez, Gershon Kedem, Clay Gloster. itc 1989: 264-274

A Framework and Method for Hierarchical Test GenerationJohn D. Calhoun, Franc Brglez. itc 1989: 480-490

Boundary scan with built-in self-testClay S. Gloster Jr., Franc Brglez. dt, 6(1):36-44, 1989. [doi]

1988

A modular scan-based testability systemFranc Brglez, David Bryan, John D. Calhoun, Robert Lisanke. iccd 1988: 408-412 [doi]

Boundary Scan with Cellular-Based Built-In Self-TestClay Gloster, Franc Brglez. itc 1988: 138-145

McMAP: a fast technology mapping procedure for multi-level logic synthesisRobert Lisanke, Franc Brglez, Gershon Kedem. iccd 1988: 252-256 [doi]

1987

Testability-Driven Random Test-Pattern GenerationRobert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory. tcad, 6(6):1082-1087, 1987. [doi]

Accelerated Transition Fault SimulationMichael H. Schultz, Franc Brglez. dac 1987: 237-243 [doi]

1985

A Fast Fault Grader: Analysis and ApplicationsFranc Brglez. itc 1985: 785-794

Fault Coverage Tools: Case StudiesFranc Brglez. itc 1985: 797-800

1984

Applications of Testability Analysis: From ATPG to Critical Delay Path TracingFranc Brglez, Philip Pownall, Robert Hum. itc 1984: 705-712

1981

Digital Signal Processing Considerations in Filter-Codec TestingFranc Brglez. itc 1981: 193-202

A set of programs for MOS designG. Sakauye, Anna Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Y. Shew, E. Attfield, Franc Brglez, Philip S. Wilcox. dac 1981: 435-442 [doi]

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2017

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1992

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1981

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