Abstract is missing.
- Collapsing the Transistor Chain to an Effective Single Equivalent TransistorAlexander Chatzigeorgiou, Spiridon Nikolaidis. 2-6 [doi]
- Design of Fault-Secure Parity-Prediction Booth MultipliersMichael Nicolaidis, Ricardo de Oliveira Duarte. 7-14 [doi]
- PASTEL: A Parameterized Memory Characterization SystemKimihiro Ogawa, Michinari Kohno, Fusako Kitamura. 15 [doi]
- Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS SystemJesper Grode, Peter Voigt Knudsen, Jan Madsen. 22-27 [doi]
- Hardware Software Partitioning with Integrated Hardware Design Space ExplorationVinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri. 28-35 [doi]
- Generation of Interconnect Topologies for Communication SynthesisMichael Gasteier, Manfred Glesner, Michael Münch. 36 [doi]
- The Design of an Asynchronous VHDL SynthesizerSun-Yen Tan, Stephen B. Furber, Wen-Fang Yen. 44-51 [doi]
- Repartitioning and Technology-Mapping of Electronic Hybrid SystemsChristoph Grimm, Klaus Waldschmidt. 52-58 [doi]
- VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive EngineeringEduard Moser, Norbert Mittwollen. 59 [doi]
- Scheduling and Module Assignment for Reducing Bist ResourcesIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer. 66-73 [doi]
- An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test SynthesisLaurence Tianruo Yang, Zebo Peng. 74-81 [doi]
- RAM-Based FPGA s: A Test Approach for the Configurable LogicMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 82-88 [doi]
- Novel Technique for Testing FPGAsCecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi. 89 [doi]
- ATM Traffic Shaper: ATSJuan Carlos Diaz, Pierre Plaza, Jesus Crespo. 96-101 [doi]
- XFVHDL: A Tool for the Synthesis of Fuzzy Logic ControllersE. Lago, Carlos J. Jiménez, D. R. Lopez, Santiago Sánchez-Solano, Angel Barriga Barrios. 102-107 [doi]
- High Speed Neural Network Chip for Trigger Purposes in High Energy PhysicsWolfgang Eppler, Thomas Fischer, Hartmut Gemmeke, A. Menchikov. 108 [doi]
- CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System ArchitecturesBharat P. Dave, Niraj K. Jha. 118-124 [doi]
- Stream Communication between Real-Time Tasks in a High-Performance MultiprocessorJeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess. 125-131 [doi]
- Scheduling of Conditional Process Graphs for the Synthesis of Embedded SystemsPetru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop. 132 [doi]
- Model Abstraction for Formal VerificationYee-Wing Hsieh, Steven P. Levitan. 140-147 [doi]
- VHDL Modelling and Analysis of Fault Secure SystemsJason Coppens, Dhamin Al-Khalili, Come Rozon. 148-152 [doi]
- Register Transfer Level VHDL Models without ClocksMatthias Mutz. 153-158 [doi]
- Parallel VHDL SimulationEdwin Naroska. 159 [doi]
- Testing DSP Cores Based on Self-Test ProgramsWei Zhao, Christos A. Papachristou. 166-172 [doi]
- Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMsVyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich. 173-179 [doi]
- Built-In Self-Test with an Alternating OutputT. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian. 180 [doi]
- From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT AlgorithmsClaus Schneider, Martin Kayss, Thomas Hollstein, Jürgen Deicke. 186-190 [doi]
- Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia CommunicationsA. M. Rassau, T. C. B. Yu, H. Cheung, Stefan Lachowicz, Kamran Eshraghian, W. A. Crossland, T. D. Wilkinson. 191-195 [doi]
- VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet TransformIsidoro Urriza, José I. Artigas, José I. García-Nicolás, Luis A. Barragan, Denis Navarro. 196 [doi]
- A Model for System-Level Timed Analysis and ProfilingAlberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto. 204-210 [doi]
- Efficient Compilation of Process-Based Concurrent Programs without Run-Time SchedulingBill Lin. 211-217 [doi]
- A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning ProcessJ. A. Maestro, Daniel Mozos, Hortensia Mecha. 218-225 [doi]
- A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration EnvironmentJoachim Gerlach, Wolfgang Rosenstiel. 226 [doi]
- Object-Oriented Modelling of Parallel Hardware SystemsGuido Schumacher, Wolfgang Nebel. 234-241 [doi]
- A Flexible Message Passing Mechanism for Objective VHDLWolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel. 242-249 [doi]
- Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDLMichael Mrva. 250-256 [doi]
- Formal Specification in VHDL for Hardware VerificationRalf Reetz, Klaus Schneider, Thomas Kropf. 257 [doi]
- A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data PathsAnna Antola, Vincenzo Piuri, Mariagiovanna Sami. 266-272 [doi]
- Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor ArraysLi-C. Wang, Magdy S. Abadir, Jing Zeng. 273-277 [doi]
- Functional Scan Chain TestingDouglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee. 278 [doi]
- Design Methodologies for System Level IPGrant Martin. 286-289 [doi]
- IP-Based System-on-a-Chip DesignBart de Loore. 290 [doi]
- A Systematic Analysis of Reuse Strategies for Design of Electronic CircuitsManfred Koegst, Dieter Garte, Peter Conradi, Michael G. Wahl. 292-296 [doi]
- VHDL Teamwork, Organization Units and Workspace ManagementSerafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba. 297-302 [doi]
- An Object-Oriented Model for Specification, Prototyping, Implementation and ReuseJörg Böttger, Karlheinz Agsteiner, Dieter Monjau, Sören Schulze. 303 [doi]
- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor ChipsetJürgen Koehl, Ulrich Baur, Thomas Ludwig 0004, Bernhard Kick, Thomas Pflueger. 312-320 [doi]
- Algorithms for Detailed Placement of Standard CellsJens Vygen. 321-324 [doi]
- Timing Analysis and Optimization of a High-Performance CMOS Processor ChipsetUwe Fassnacht, Jürgen Schietke. 325-331 [doi]
- A Sequential Detailed Router for Huge Grid GraphsAsmus Hetzel. 332 [doi]
- Reconfigurable Logic for Systems on a ChipW. Shields Neely. 340 [doi]
- An Energy-Conscious Exploration Methodology for Reconfigurable DSPsJan M. Rabaey, Marlene Wan. 341-342 [doi]
- Design Of Future SystemsIan Page. 343 [doi]
- AFTA: A Formal Delay Model for Functional Timing AnalysisV. Chandramouli, Jesse Whittemore, Karem A. Sakallah. 350-355 [doi]
- Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-OffsDirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebel, Carl von Ossietzky. 356-361 [doi]
- Advanced Optimistic Approaches in Logic SimulationS. Schmerler, Y. Tanurhan, Klaus D. Müller-Glaser. 362 [doi]
- PSCP: A Scalable Parallel ASIP Architecture for Reactive SystemsAndreas Pyttel, Alexander Sedlmeier, Christian Veith. 370-376 [doi]
- A Constraint Driven Approach to Loop Pipelining and Register BindingBart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess. 377-383 [doi]
- Multiple Behavior Module Synthesis Based on Selective GroupingsJu Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung. 384-388 [doi]
- Optimal Temporal Partitioning and Synthesis for Reconfigurable ArchitecturesMeenakshi Kaul, Ranga Vemuri. 389 [doi]
- An Effective General Connectivity Concept for ClusteringJianjian Song, Zhaoxuan Shen, Wenjun Zhuang. 398-405 [doi]
- Improved Approximation Bounds for the Group Steiner ProblemChristopher S. Helvig, Gabriel Robins, Alexander Zelikovsky. 406-413 [doi]
- An Interactive Router for Analog IC DesignThorsten Adler, Juergen Schaeuble. 414 [doi]
- Formal Verification: A New Standard CAD Tool for the Industrial Design FlowWolfgang Rosenstiel. 422 [doi]
- A System-Level Co-Verification Environment for ATM Hardware DesignGuido Post, Andrea Müller, Thorsten Grötker. 424-428 [doi]
- FRIDGE: A Fixed-Point Design and Simulation EnvironmentHolger Keding, Markus Willems, Martin Coors, Heinrich Meyr. 429-435 [doi]
- Verification by Simulation Comparison using Interface SynthesisCordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel. 436 [doi]
- Layout-Driven High Level Synthesis for FPGA Based ArchitecturesMin Xu, Fadi J. Kurdahi. 446-450 [doi]
- Cross-Level Hierarchical High-Level SynthesisOliver Bringmann, Wolfgang Rosenstiel. 451-456 [doi]
- An Algorithm To Determine Mutually Exclusive Operations In Behavioral DescriptionsJian Li, Rajesh K. Gupta. 457 [doi]
- A Performance-Driven MCM Router with Special Consideration of Crosstalk ReductionDongsheng Wang, Ernest S. Kuh. 466-470 [doi]
- Interconnect Tuning Strategies for High-Performance IcsAndrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma. 471-478 [doi]
- A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire SizingChris C. N. Chu, D. F. Wong. 479 [doi]
- Next Generation System Level Design ToolsWolfgang Rosenstiel. 488 [doi]
- Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICsRosa Rodríguez-Montañés, Joan Figueras. 490-494 [doi]
- A Fully Digital Controlled Off-Chip IDDQ Measurement UnitB. Straka, Hans A. R. Manhaeve, Jozef Vanneuville, M. Svajda. 495-500 [doi]
- March Tests for Word-Oriented MemoriesA. J. van de Goor, Issam B. S. Tlili. 501 [doi]
- A Modeling Approach to Include Mechanical Microsystem Components into the System SimulationR. Neul, U. Becker, G. Lorenz, P. Schwarz, J. Haase, S. Wünsche. 510-217 [doi]
- Fast Field Solvers for Thermal and Electrostatic AnalysisVladimir Székely, Márta Rencz. 518-523 [doi]
- Microsystems Testing: an Approach and Open ProblemsMarcelo Lubaszewski, Érika F. Cota, Bernard Courtois. 524 [doi]
- Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade ApproximationRoland W. Freund, Peter Feldmann. 530-537 [doi]
- An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect ModelsNuno Alexandre Marques, Mattan Kamon, Jacob White, Luis Miguel Silveira. 538-543 [doi]
- MCM Interconnect Design Using Two-Pole ApproximationJianhua Shao, Richard M. M. Chen. 544 [doi]
- Design-Manufacturing Interface: Part I - VisionWojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare. 550-556 [doi]
- Design-Manufacturing Interface: Part II - ApplicationsWojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon. 557-562 [doi]
- Performance - Manufacturability Tradeoffs in IC DesignHans T. Heineken, Wojciech Maly. 563 [doi]
- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level TechniquesElizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 570-576 [doi]
- State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential CircuitsMichael S. Hsiao, Srimat T. Chakradhar. 577-582 [doi]
- Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector RestorationRuifeng Guo, Irith Pomeranz, Sudhakar M. Reddy. 583 [doi]
- Architectural Simulation in the Context of Behavioral SynthesisA. Jemai, Polen Kission, Ahmed Amine Jerraya. 590-595 [doi]
- Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication ProtocolsJohnny Öberg, Ahmed Hemani, Anshul Kumar. 596 [doi]
- Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICsSamuel Norman Hamilton, Alex Orailoglu. 604 [doi]
- Dynamic Minimization of Word-Level Decision DiagramsStefan Höreth, Rolf Drechsler. 612-617 [doi]
- Sequential Equivalence Checking without State Space TraversalC. A. J. van Eijk. 618-623 [doi]
- On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level CircuitsLluis Ribas, Jordi Carrabina. 624 [doi]
- Silicon Debug of Systems-on-Chips632 [doi]
- Hierarchical Characterization of Analog Integrated CMOS CircuitsJosef Eckmueller, Martin Groepl, Helmut E. Graeb. 636-643 [doi]
- EASY - a System for Computer-Aided Examination of Analog CircuitsG. Droege, M. Thole, Ernst-Helmut Horneber. 644-648 [doi]
- A Formal Approach to Verification of Linear Analog Circuits with Parameter TolerancesLars Hedrich, Erich Barke. 649 [doi]
- Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to BenchmarkingDebabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III. 656-663 [doi]
- Technology Mapping for Minimizing Gate and Routing AreaAiguo Lu, Guenter Stenz, Frank M. Johannes. 664-669 [doi]
- Exploiting Symbolic Techniques for Partial Scan Flip Flop SelectionFulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante. 670 [doi]
- Temperature Effect on Delay for Low Voltage ApplicationsJean Michel Daga, E. Ottaviano, Daniel Auvergne. 680-685 [doi]
- Data Driven Power Optimization of Sequential CircuitsQi Wang, Sarma B. K. Vrudhula. 686-691 [doi]
- Gated Clock Routing Minimizing the Switched CapacitanceJaewon Oh, Massoud Pedram. 692-697 [doi]
- Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS CircuitsYi-Min Jiang, Kwang-Ting Cheng. 698 [doi]
- Embedded DRAM Architectural Trade-OffsNorbert Wehn, Søren Hein. 704-708 [doi]
- Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology SolutionsFrancky Catthoor. 709 [doi]
- Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to SiliconJan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen. 716-720 [doi]
- A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional BlocksR. Rosenberger, Sorin A. Huss. 721-728 [doi]
- Switching Response Modeling of the CMOS Inverter for Sub-micron DevicesLabros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis. 729 [doi]
- On Removing Multiple Redundancies in Combinational CircuitsDavid Ihsin Cheng. 738-742 [doi]
- Multi-output Functional Decomposition with Exploitation of Don t CaresChristoph Scholl. 743-748 [doi]
- An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic MinimizationJ. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren. 749-754 [doi]
- Restructuring Logic Representations with Easily Detectable Simple Disjunctive DecompositionsHiroshi Sawada, Shigeru Yamashita, Akira Nagoya. 755 [doi]
- Power Estimation of Behavioral DescriptionsFabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino. 762-766 [doi]
- Characterization-Free Behavioral Power ModelingAlessandro Bogliolo, Luca Benini, Giovanni De Micheli. 767-773 [doi]
- Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power EstimationDiana Marculescu, Radu Marculescu, Massoud Pedram. 774 [doi]
- Efficient Verification using Generalized Partial Order AnalysisSteven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin. 782-789 [doi]
- Efficient Encoding Schemes for Symbolic Analysis of Petri NetsEnric Pastor, Jordi Cortadella. 790-795 [doi]
- Propagation of Last-Transition-Time Constraints in Gate-Level Timing AnalysisMaroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel. 796-802 [doi]
- Combinational Verification based on High-Level Functional SpecificationsEvguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton. 803 [doi]
- Switch-Level Fault Coverage Analysis for Switched-Capacitor SystemsSalvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas. 810-814 [doi]
- Optimized Implementations of the Multi-Configuration DFT Technique for Analog CircuitsMichel Renovell, Florence Azaïs, Yves Bertrand. 815-821 [doi]
- Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic FaultsWalter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb. 822 [doi]
- A New Paradigm for Dichotomy-based Constrained EncodingOlivier Coudert. 830-834 [doi]
- A Dynamic Model for the State Assignment ProblemManuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas. 835-839 [doi]
- Efficient Minarea Retiming of Large Level-Clocked CircuitsNaresh Maheshwari, Sachin S. Sapatnekar. 840 [doi]
- IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive CircuitsKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. 848-854 [doi]
- Instruction Scheduling for Power Reduction in Processor-Based System DesignHiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura. 855-860 [doi]
- Address Bus Encoding Techniques for System-Level Power OptimizationLuca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano. 861 [doi]
- A Scalable Architecture for Multi-threaded JAVA ApplicationsMichael Mrva, Klaus Buchenrieder, Rainer Kress. 868-874 [doi]
- Hardware/Software Co-Design of a Fuzzy RISC ProcessorValentina Salapura, Michael Gschwind. 875-882 [doi]
- Innovative System-level Design Environment Based on FORM for Transport Processing SystemKazushige Higuchi, Kazuhiro Shirakawa. 883 [doi]
- Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC sJoao Paulo Costa, Mike Chou, L. Miguel Silveira. 892-898 [doi]
- Efficient DC Fault Simulation of Nonlinear Analog CircuitsMichael W. Tian, C.-J. Richard Shi. 899-904 [doi]
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog CircuitsJuan A. Prieto, Adoración Rueda, Ian A. Grout, Eduardo J. Peralías, José L. Huertas, Andrew M. D. Richardson. 905 [doi]
- Synthesis of Communicating Controllers for Concurrent Hardware/Software SystemsR. Niemann, Peter Marwedel. 912-913 [doi]
- A Knowledge-based System for Hardware-Software PartitioningMarisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López. 914-915 [doi]
- A Formal Description of VHDL-AMS Analogue SystemsTom J. Kazmierski. 916-920 [doi]
- Scanning Datapaths: A Fast and Effective Partial Scan Selection TechniqueMarie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe. 921-922 [doi]
- Universal Strong Encryption FPGA Core ImplementationDavor Runje, Mario Kovac. 923-924 [doi]
- Data Cache Sizing for Embedded Processor ApplicationsPreeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau. 925-926 [doi]
- A Programmable Multi-Language Generator for CoDesignJean Paul Calvez, Dominique Heller, F. Muller, Olivier Pasquier. 927-928 [doi]
- Register-Constrained Address Computation in DSP ProgramsAnupam Basu, Rainer Leupers, Peter Marwedel. 929-930 [doi]
- Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid BaseThomas Müller-Wipperfürth, Richard Hagelauer. 931-932 [doi]
- AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital SystemsGeorge Economakos, George K. Papakonstantinou, Panayotis Tsanakas. 933-934 [doi]
- Static Analysis Tools for Soft-Core Reviews and AuditsSerafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez. 935-936 [doi]
- A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic ProcessorMichael G. Wahl, Holger Völkel. 937-938 [doi]
- A Comparing Study of Technology Mapping for FPGAHans-Georg Martin, Wolfgang Rosenstiel. 939-940 [doi]
- Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulationTom J. Kazmierski. 941-944 [doi]
- Optimized Timed Hardware Software Cosimulation without Roll-backWonyong Sung, Soonhoi Ha. 945-946 [doi]
- A Cell and Macrocell Compiler for GaAs VLSI Full-Custom DesignJuan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez. 947-948 [doi]
- Architectural Rule Checking for High-level SynthesisJie Gong, Chih-Tung Chen, Kayhan Küçükçakar. 949-950 [doi]
- A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit SimulatorHideaki Kimura, Norihito Iyenaga. 951-952 [doi]
- Core Interconnect Testing HazardsPetra Nordholz, Hartmut Grabinski, Dieter Treytnar, Jan Otterstedt, Dirk Niggemeyer, Uwe Arz, T. W. Williams. 953-954 [doi]
- Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error ModelsTeresa Riesgo, Yago Torroja, Eduardo de la Torre, J. Uceda. 955-956 [doi]
- Fault Analysis in Networks with Concurrent Error Detection PropertiesCristiana Bolchini, Fabio Salice, Donatella Sciuto. 957-958 [doi]
- IOCIMU - An Integrated Off-Chip IDDQ Measurement UnitM. Svajda, B. Straka, Hans A. R. Manhaeve. 959-960 [doi]
- Automatic Topology Optimization for Analog Module GeneratorsMarkus Wolf, Ulrich Kleine. 961-962 [doi]
- Asynchronous Scheduling and AllocationAnatoly Prihozhy. 963-964 [doi]
- Path Verification Using Boolean SatisfiabilityMatthias Ringe, Thomas Lindenkreuz, Erich Barke. 965-966 [doi]
- PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean ExpressionsSumit Roy, Harm Arts, Prithviraj Banerjee. 967-968 [doi]
- Power and Timing Modeling for ASIC DesignsWolfgang Roethig, A. M. Zarkesh, M. Andrews. 969-970 [doi]
- Constraints Space Management for the Layout of Analog IC sBogdan G. Arsintescu, Ralph H. J. M. Otten. 971-972 [doi]
- A Synthesis Procedure for Flexible Logic FunctionsIrith Pomeranz, Sudhakar M. Reddy. 973-974 [doi]
- Denotational Semantics of a Behavioral Subset of VHDLFelix Nicoli. 975-976 [doi]
- Correct High-Level Synthesis: a Formal PerspectiveJosé M. Mendías, Román Hermida. 977-978 [doi]
- A Bypass Scheme for Core-Based System Fault TestingMehrdad Nourani, Christos A. Papachristou. 979-980 [doi]
- Highly Testable and Compact 1-out-of-n Code Checker with Single OutputCecilia Metra, Michele Favalli, Bruno Riccò. 981-982 [doi]
- Design-for-Testability for Synchronous Sequential Circuits using Locally Available LinesIrith Pomeranz, Sudhakar M. Reddy. 983-984 [doi]
- CMOS Combinational Circuit Sizing by Stage-wise TaperingSatyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija. 985-988 [doi]
- Fault Detection for Linear Analog Circuits Using Current InjectionJaime Velasco-Medina, Th. Calin, Michael Nicolaidis. 987 [doi]