Ganesh Lakshminarayana - researchr alias

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Viewing Publication 1 - 48 from 48

2006

The LOTTERYBUS on-chip communication architectureKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana. tvlsi, 14(6):596-608, 2006. [doi]

2005

Memory binding for performance optimization of control-flow intensive behavioral descriptionsKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. tvlsi, 13(5):513-524, 2005. [doi]

Input space-adaptive optimization for embedded-software synthesisWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. tcad, 24(11):1677-1693, 2005. [doi]

2004

2003

Analysis of power dissipation in embedded systems using real-time operating systemsRobert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. tcad, 22(5):615-627, 2003. [doi]

2002

2001

LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip DesignsKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana. dac 2001: 15-20 [doi]

Accurate Power Macro-modeling Techniques for Complex RTL CircuitsNachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar. vlsid 2001: 235-241 [doi]

Transient Power Management Through High Level SynthesisVijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana. iccad 2001: 545-552 [doi]

TAO: regular expression-based register-transfer level testability analysis and optimizationSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. tvlsi, 9(6):824-832, 2001. [doi]

Testing of core-based systems-on-a-chipSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. tcad, 20(3):426-439, 2001. [doi]

High-level Software Energy Macro-modelingTat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. dac 2001: 605-610 [doi]

Input Space Adaptive Design: A High-level Methodology for Energy and Performance OptimizationWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. dac 2001: 738-743 [doi]

2000

Power analysis of embedded operating systemsRobert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. dac 2000: 312-315 [doi]

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chipsKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey. dac 2000: 513-518 [doi]

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designsGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. tcad, 19(3):308-324, 2000. [doi]

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability AnalysisGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. TC, 49(9):865-885, 2000. [doi]

Integrating variable-latency components into high-level synthesisVijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana. tcad, 19(10):1105-1117, 2000. [doi]

High-Level Synthesis with Variable-Latency ComponentsVijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana. vlsid 2000: 220-227 [doi]

: Reducing test application time in high-level test generationSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. itc 2000: 829-838

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuitsSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. tcad, 19(8):894-906, 2000. [doi]

1999

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systemsBharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha. tvlsi, 7(1):92-104, 1999. [doi]

Memory binding for performance optimization of control-flow intensive behaviorsKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. iccad 1999: 482-488 [doi]

High-level synthesis of low-power control-flow intensive circuitsKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. tcad, 18(12):1715-1729, 1999. [doi]

FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptionsGanesh Lakshminarayana, Niraj K. Jha. tcad, 18(11):1577-1594, 1999. [doi]

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviorsGanesh Lakshminarayana, Niraj K. Jha. tcad, 18(3):265-281, 1999. [doi]

Wavesched: a novel scheduling technique for control-flow intensive designsGanesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha. tcad, 18(5):505-523, 1999. [doi]

Power management in high-level synthesisGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey. tvlsi, 7(1):7-15, 1999. [doi]

Common-Case Computation: A High-Level Technique for Power and Performance OptimizationGanesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey. dac 1999: 56-61 [doi]

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BISTSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. vts 1999: 398-406 [doi]

A framework for testing core-based systems-on-a-chipSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. iccad 1999: 385-390 [doi]

1998

Fast high-level power estimation for control-flow intensive designKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. islped 1998: 299-304 [doi]

IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive CircuitsKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. date 1998: 848-854 [doi]

Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral DescriptionsGanesh Lakshminarayana, Niraj K. Jha. dac 1998: 439-444 [doi]

::::FACT::::: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral DescriptionsGanesh Lakshminarayana, Niraj K. Jha. dac 1998: 102-107 [doi]

Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral DescriptionsGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. dac 1998: 108-113 [doi]

A Power Management Methodology for High-Level SynthesisGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey. vlsid 1998: 24-19

Transforming control-flow intensive designs to facilitate power managementGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey. iccad 1998: 657-664 [doi]

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptionsSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. iccad 1998: 577-584 [doi]

TAO: regular expression based high-level testability analysis and optimizationSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. itc 1998: 331-340 [doi]

1997

COSYN: Hardware-Software Co-Synthesis of Embedded SystemsBharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha. dac 1997: 703-708 [doi]

Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptionsGanesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha. iccad 1997: 244-250 [doi]

1996

Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability AnalysisGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. ftcs 1996: 336-345

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2006

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1996

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