Abstract is missing.
- Case-based reasoning: diagnosis of faults in complex systems through reuse of experienceL. Derere. 27-34
- On-line and off-line test of airborne digital systems: a reliability studyJacob Savir. 35-44
- The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environmentStephen Harrison, Peter Collins, Greg Noeninckx. 45-54
- Bridging the gap between embedded test and ATEMartin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras. 55-63
- Doing it in STIL: intelligent conversion from STIL to an ATE formatBruce R. Parnas. 64-71
- Easy mixed signal test creation with test elements and proceduresAndy Kittross. 72-79
- Optical interferometric probing of advanced microprocessorsTravis M. Eiles, Keneth R. Wilsher, William K. Lo, G. Xiao. 80-84
- Testing for tunneling opensChien-Mo James Li, Edward J. McCluskey. 85-94
- Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?Will Moore, Guido Gronthoud, Keith Baker, Maurice Lousberg. 95-104
- Application of deterministic logic BIST on industrial circuitsGundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen. 105-114
- Reducing test data volume using external/LBIST hybrid test patternsDebaleena Das, Nur A. Touba. 115-122
- Test structure verification of logical BIST: problems and solutionsMichael Cogswell, Don Pearl, James Sage, Alan Troidl. 123-130
- DFT advances in Motorola s Next-Generation 74xx PowerPC:::TM::: microprocessorRajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan. 131-140
- Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessorFarideh Golshan. 141-150
- The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor coreTeresa L. McLaurin, Frank Frederick. 151-159
- Si-emulation: system verification using simulation and emulationZan Yang, Byeong Min, Gwan Choi. 160-169
- A software development kit for dependable applications in embedded systemsAlfredo Benso, Silvia Chiusano, Paolo Prinetto. 170-178
- Combinational logic synthesis for diversity in duplex systemsSubhasish Mitra, Edward J. McCluskey. 179-188
- Variance reduction using wafer patterns in I_ddQ dataW. Robert Daasch, James McNames, Daniel Bockelman, Kevin Cota. 189-198
- DECOUPLE: defect current detection in deep submicron I_DDQYukio Okuda. 199-206
- Improving Delta-I_DDQ-based test methodsClaude Thibeault. 207-216
- Increasing the IDDQ test resolution using current predictionPramodchandran N. Variyam. 217-224
- Diagnostic test generation for sequential circuitsXiaoming Yu, Jue Wu, Elizabeth M. Rudnick. 225-234
- An improved fault diagnosis algorithm based on path tracing with dynamic circuit extractionKazuki Shigeta, Toshio Ishiyama. 235-244
- Path-delay fault diagnosis in non-scan sequential circuits with at-speed test applicationPankaj Pant, Abhijit Chatterjee. 245-252
- POIROT: a logic fault diagnosis tool and its applicationsSrikanth Venkataraman, Scott Brady Drummonds. 253-262
- Efficient test mode selection and insertion for RTL-BISTSubrata Roy, Gokhan Guner, Kwang-Ting Cheng. 263-272
- Deterministic partitioning techniques for fault diagnosis in scan-based BISTIsmet Bayraktaroglu, Alex Orailoglu. 273-282
- A BIST approach for very deep sub-micron (VDSM) defectsYasuo Sato, Toyohito Ikeya, Machinobu Nakao, Takaharu Nagumo. 283-291
- Test point insertion for compact test setsM. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor. 292-301
- A domain coverage metric for the validation of behavioral VHDL descriptionsQiushuang Zhang, Ian G. Harris. 302-308
- Static property checking using ATPG vs. BDD techniquesChung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng. 309-316
- On validating data hold times for flip-flops in sequential circuitsSudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta. 317-325
- Test generation for path-delay faults in one-dimensional iterative logic arraysNabil M. Abdulrazzaq, Sandeep K. Gupta. 326-335
- Stuck-fault tests vs. actual defectsEdward J. McCluskey, Chao-Wen Tseng. 336-343
- Successful implementation of structured testingRonald A. Richmond. 344-348
- Measuring code edges of ADCs using interpolation and its application to offset and gain error testingPramodchandran N. Variyam, Vinay Agrawal. 349-357
- Optimal INL/DNL testing of A/D converters using a linear modelSasikumar Cherubal, Abhijit Chatterjee. 358-366
- Optimal analog trim techniques for improving the linearity of pipeline ADCsTurker Kuyel, Frank Tsay. 367-375
- Selection of potentially testable path delay faults for test generationAtsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy. 376-384
- Enhanced delay defect coverage with path-segmentsManish Sharma, Janak H. Patel. 385-392
- On invalidation mechanisms for non-robust delay testsHaluk Konuk. 393-399
- Comparing functional and structural testsPeter C. Maxwell, Ismed Hartanto, Lee Bentz. 400-407
- An empirical study on the effects of test type ordering on overall test efficiencyJayashree Saxena, Kenneth M. Butler. 408-416
- A framework to evaluate test tradeoffs in embedded core based systems-case study on TI s TMS320C27xxJais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji. 417-425
- Industrial evaluation of DRAM SIMM testsA. J. van de Goor, A. Paalvast. 426-435
- Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyondHerold Pilo, Stu Hall, Patrick Hansen, Steve Lamphier, Chris Murphy. 436-443
- Pattern generation tools for the development of memory core test patterns for Rambus devicesJohn Privitera, Steven Woo, Craig Soldat. 444-453
- Test method evaluation experiments and dataPhil Nigh, Anne E. Gattiker. 454-463
- Defect screening challenges in the Gigahertz/Nanometer age: keeping up with the tails of defect behaviorsMike Rodgers. 464-467
- A new paradigm in test for the next millenniumJerry Katz, Rochit Rajsuman. 468-476
- Reducing device yield fallout at wafer level test with electrohydrodynamic (EHD) cleaningJerry J. Broz, James C. Andersen, Reynaldo M. Rincon. 477-484
- Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applicationsCristo da Costa. 485-491
- Analysis of interconnect crosstalk defect coverage of test setsYi Zhao, Sujit Dey. 492-501
- Identification of crosstalk switch failures in domino CMOS circuitsRahul Kundu, Ronald D. Blanton. 502-509
- Precise test generation for resistive bridging faults of CMOS combinational circuitsToshiyuki Maeda, Kozo Kinoshita. 510-519
- Non-scan design for testability for synchronous sequential circuits based on conflict analysisDong Xiang, Yi Xu, Hideo Fujiwara. 520-529
- Design and implementation of a parallel automatic test pattern generation algorithm with low test vector countRobert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton. 530-537
- Exploiting don t cares to enhance functional testsMark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr. 538-546
- Self test architecture for testing complex memory structuresKamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor. 547-556
- A programmable BIST architecture for clusters of multiple-port SRAMsAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni. 557-566
- A built-in self-repair analyzer (CRESTA) for embedded DRAMsTomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka. 567-574
- Power pin testing: making the test coverage completeFrans de Jong, Ben Kup, Rodger Schuttert. 575-584
- End-to-end testing for boards and systems using boundary scanRobert W. Barr, Chen-Huan Chiang, Edward L. Wallace. 585-592
- Motherboard testing using the PCI busDavid McClintock, Lance Cunningham, Takis Petropoulos. 593-599
- Digital serial communication device testing and its implications on automatic test equipment architectureYongming Cai, T. P. Warwick, Sunil G. Rane, E. Masserrat. 600-609
- An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memoryDieu Van Dinh, Virginia Rabitoy. 610-618
- The path to one-picosecond accuracyLuca Sartori, Burnell G. West. 619-627
- Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuitsSteven F. Oakland. 628-637
- Using on-chip test pattern compression for full scan SoC designsHelmut Lang, Jens Pfeiffer, Jeff Maguire. 638-643
- Non-intrusive BIST for systems-on-a-chipSilvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich. 644-651
- Low power BIST design by hypergraph partitioning: methodology and architecturesPatrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch. 652-661
- Power conscious test synthesis and scheduling for BIST RTL data pathsNicola Nicolici, Bashir M. Al-Hashimi. 662-671
- BISTing data paths at behavioral levelDavid Berthelot, Marie-Lise Flottes, Bruno Rouzeyre. 672-680
- Optimizing the flattened test-generation model for very large designsPeter Wohl, John A. Waicukauski. 681-690
- Conversion of small functional test sets of nonscan blocks to scan patternsDon E. Ross, Tim Wood, Grady Giles. 691-700
- Logic mapping on a microprocessorAnjali Kinra, Hari Balachandran, Regy Thomas, John Carulli. 701-710
- Programming of flash with ICT rights and responsibilitiesJulia A. Keahey. 711-717
- It isn t just testing anymore (REDUX)Stephen F. Scheiber. 718-723
- System issues in boundary-scan board testKenneth P. Parker. 724-728
- Computer-aided fault to defect mapping (CAFDM) for defect diagnosisZoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler. 729-738
- Analysis of failure sources in surface-micromachined MEMSNilmoni Deb, Ronald D. Blanton. 739-749
- A scalable and efficient methodology to extract two node bridges from large industrial circuitsSujit T. Zachariah, Sreejit Chakravarty. 750-759
- Bridging fault extraction from physical design data for manufacturing test developmentCharles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic. 760-769
- On using IEEE P1500 SECT for test plug-n-playYervant Zorian, Erik Jan Marinissen, Rohit Kapur. 770-777
- A mixed mode BIST scheme based on reseeding of folding countersSybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang. 778-784
- DIST-based detection and diagnosis of multiple faults in FPGAsMiron Abramovici, Charles E. Stroud. 785-794
- Novel technique for built-in self-test of FPGA interconnectsXiaoling Sun, Jian Xu, Ben Chan, Pieter M. Trouborst. 795-803
- Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift registerXrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos. 804-811
- Universal test generation using fault tuplesRao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton. 812-819
- Fault distinguishing pattern generationThomas Bartenstein. 820-828
- : Reducing test application time in high-level test generationSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. 829-838
- MUST: multiple-stem analysis for identifying sequentially untestable faultsQiang Peng, Miron Abramovici, Jacob Savir. 839-846
- Streamlining programmable device and system test using IEEE Std 1532Neil G. Jacobson. 847-853
- Different experiments in test generation for XILINX FPGAsMichel Renovell, Yervant Zorian. 854-862
- Adapting scan architectures for low power operationLee Whetsel. 863-872
- Optimization trade-offs for vector volume and test powerBahram Pouya, Alfred L. Crouch. 873-881
- A comparison of classical scheduling approaches in power-constrained block-test schedulingValentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu. 882-891
- HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCsAlfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian. 892-901
- An ILP formulation to optimize test access mechanism in system-on-chip testingMehrdad Nourani, Christos A. Papachristou. 902-910
- Wrapper design for embedded core testYervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel. 911-920
- Deception by design: fooling ourselves with gate-level modelsPeter C. Maxwell, Jeff Rearick. 921-929
- Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-DJennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer. 930-939
- Register-transfer level fault modeling and test evaluation techniques for VLSI circuitsPradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul. 940-949
- Microwave test mismatch and power de-embeddingPeter M. Higgins, Jim Lampos. 950-954
- Jitter measurements of a PowerPC:::TM::: microprocessor using an analytic signal methodTakahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe. 955-964
- Technique for testing a very high speed mixed signal read channel designDoug Matthes, John Ford. 965-970
- Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection techniqueRamesh Karri, Kaijie Wu. 971-978
- Concurrent error detection in block ciphersSantiago Fernández-Gomez, Juan J. RodrÃguez-Andina, Enrique Mandado. 979-984
- Which concurrent error detection scheme to choose ?Subhasish Mitra, Edward J. McCluskey. 985-994
- Device interfacing: the weakest link in the chain to break into the giga bit domain?Ulrich Schoettmer, Chris Wagner, Tom Bleakley. 995-1004
- Structural test in a board self test environmentUlf Pillkahn. 1005-1012
- Challenges of high supply currents during VLSI testGerald H. Johnson. 1013-1020
- Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysisJiun-Lang Huang, Kwang-Ting Cheng. 1021-1030
- A stand-alone integrated test core for time and frequency domain measurementsMohamed Hafed, Nazmy Abaskharoun, Gordon W. Roberts. 1031-1040
- Digital signature proposal for mixed-signal circuitsAnna Maria Brosa, Joan Figueras. 1041-1050
- Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQAli Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De. 1051-1059
- An analysis of the delay defect detection capability of the ECR test methodSeonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota. 1060-1069
- Predicting device performance from pass/fail transient signal analysis dataJames F. Plusquellic, Amy Germida, Jonathan Hudson, Ernesto Staroswiecki, Chintan Patel. 1070-1079
- Test program synthesis for path delay faults in microprocessor coresWei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng. 1080-1089
- A good excuse for reuse: open TAP controller designDavid B. Lavo. 1090-1099
- On-the-shelf core pattern methodology for ColdFire(R) microprocessor coresTeresa L. McLaurin, John C. Potter. 1100-1107
- Current ratios: a self-scaling technique for production IDDQ testingPeter C. Maxwell, Pete O Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman. 1148-1156