Stephen Pateras - researchr alias

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Viewing Publication 1 - 11 from 11

2004

Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having BothStephen Pateras. itc 2003: 1413 [doi]

2003

Achieving At-Speed Structural TestStephen Pateras. dt, 20(5):26-33, 2003. [doi]

2002

Embedded Diagnosis IPStephen Pateras. date 2002: 242-243 [doi]

IP for Embedded DiagnosisStephen Pateras. dt, 19(3):46-55, 2002. [doi]

2000

Bridging the gap between embedded test and ATEMartin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras. itc 2000: 55-63

1999

An embedded technique for at-speed interconnect testingBenoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras. itc 1999: 431-438

1997

Advanced microprocessor test strategy and methodologyWilliam V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko, Stephen Pateras, Dale E. Hoffman, Timothy G. McNamara, Thomas J. Snethen. ibmrd, 41(4&5):611-628, 1997. [doi]

1995

Avoiding Unknown States When Scanning Mutually Exclusive LatchesStephen Pateras, Martin S. Schmookler. itc 1995: 311-318

1991

Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level CircuitsStephen Pateras, Janusz Rajski. itc 1991: 473-482

Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level CircuitsStephen Pateras, Janusz Rajski. dac 1991: 347-352 [doi]

1988

A self-reconfiguration scheme for fault-tolerant VLSI processor arraysStephen Pateras, Janusz Rajski. iccd 1988: 560-563 [doi]

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