Thomas J. Snethen - researchr alias

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Viewing Publication 1 - 13 from 13

2014

Efficient testing of hierarchical core-based SOCsBrion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen. itc 2014: 1-10 [doi]

2010

Low cost at-speed testing using On-Product Clock Generation compatible with test compressionBrion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise. itc 2010: 724-733 [doi]

2009

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay TestAnis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai. jolpe, 5(4):520-528, 2009. [doi]

2007

Using Programmable On-Product Clock Generation (OPCG) for Delay TestBrion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen. ats 2007: 69-72 [doi]

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generationAnis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise. itc 2007: 1-10 [doi]

2001

A SmartBIST Variant with Guaranteed EncodingBernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater. ats 2001: 325 [doi]

1999

A Simplified Method for Testing the IBM Pipeline Partial-Scan MicroprocessorXinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther. ats 1999: 321-326 [doi]

1998

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chipMary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott. itc 1998: 717-726 [doi]

1997

Advanced microprocessor test strategy and methodologyWilliam V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko, Stephen Pateras, Dale E. Hoffman, Timothy G. McNamara, Thomas J. Snethen. ibmrd, 41(4&5):611-628, 1997. [doi]

1996

A weighted random pattern test generation systemRohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams. tcad, 15(8):1020-1025, 1996. [doi]

1994

Design of an Efficient Weighted-Random-Pattern Generation SystemRohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams. itc 1994: 491-500

1977

Simulator-oriented fault test generatorThomas J. Snethen. dac 1977: 88-93 [doi]

1970

Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilitiesManuel Correia, Donald Cossman, Franco Putzolu, Thomas J. Snethen. dac 1970: 100-107 [doi]

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