Table of Contents

• Keynote Speech 1: New Paths for TestJacob Abraham. 3 [doi]
• Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on TestSanjiv Taneja. 4-5 [doi]
• Invited Talk 1: Testing of Power Constraint ComputingT. M. Mak. 6 [doi]
• Invited Talk 2: EDA to the Rescue of the Silicon RoadmapT. W. Williams. 7-8 [doi]
• Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced TechnologyKary Chien. 9 [doi]
• The Region-Exhaustive Fault ModelAbhijit Jas, Suriyaprakash Natarajan, Srinivas Patil. 13-18 [doi]
• Mining Sequential Constraints for Pseudo-Functional TestingWeixin Wu, Michael S. Hsiao. 19-24 [doi]
• Estimating the Fault Coverage of Functional Test Sequences Without Fault SimulationIrith Pomeranz, Praveen Parvathala, Srinivas Patil. 25-32 [doi]
• Fast Bridging Fault Diagnosis using Logic InformationAlexandre Rousset, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 33-38 [doi]
• Clues for Modeling and Diagnosing Open Faults with Considering Adjacent LinesHiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume. 39-44 [doi]
• Fault Dictionary Based Scan Chain Failure DiagnosisRuifeng Guo, Yu Huang 0005, Wu-Tung Cheng. 45-52 [doi]
• Test Education in the Global EconomyT. Cheng, J. Abraham, S. Mir, Yinghua Min, J. Wang, Cheng-Wen Wu. 53 [doi]
• Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay FaultsShahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer. 57-64 [doi]
• False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay FaultsYuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara. 65-68 [doi]
• Using Programmable On-Product Clock Generation (OPCG) for Delay TestBrion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen. 69-72 [doi]
• An On-Line BIST Technique for Delay Fault Detection in CMOS CircuitsElham K. Moghaddam, Shaahin Hessabi. 73-78 [doi]
• A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR ReseedingSeongmoon Wang, Wenlong Wei, Srimat T. Chakradhar. 79-86 [doi]
• Test Compression / Decompression Based on JPEG VLC AlgorithmHideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue. 87-90 [doi]
• A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector DecomposAiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani. 91-94 [doi]
• Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan ArchitectureSying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li. 95-100 [doi]
• Resistive Bridging Faults DFT with Adaptive Power Management AwarenessUrban Ingelsson, Paul M. Rosinger, S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod. 101-106 [doi]
• Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATEDan Zhao, Ronghua Huang, Hideo Fujiwara. 107-110 [doi]
• An Efficient Peak Power Reduction Technique for Scan TestingMeng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang. 111-114 [doi]
• High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for InterconnectsSunghoon Chun, YongJoon Kim, Sungho Kang. 115-120 [doi]
• A RTL Testability Analyzer Based on Logical Virtual PrototypingYu Huang 0005, Nilanjan Mukherjee 0001, Wu-Tung Cheng, Greg Aldrich. 121-124 [doi]
• Optimum Test Set for Bridging Fault Detection in Reversible CircuitsHafizur Rahaman 0001, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya. 125-128 [doi]
• Layout-Aware Multi-Layer Multi-Level Scan Tree SynthesisSying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li. 129-134 [doi]
• A Test and Diagnosis Methodology for RF TransceiversHung-Kai Chen 0001, Chauchin Su. 135-138 [doi]
• Fourier Spectrum-Based Signature Test: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test ResourcesGanesh Srinivasan, Abhijit Chatterjee, Vishwanath Natarajan. 139-142 [doi]
• A BIST Technique for RF Voltage-Controlled OscillatorsHsieh-Hung Hsieh, Yen-Chih Huang, Liang-Hung Lu, Guo-Wei Huang. 143-148 [doi]
• An Improved Test Case Generation Method of Pair-Wise TestingFeng-An Qian, Jian-Hui Jiang. 149-154 [doi]
• System Testing using UML ModelsMonalisa Sarma, Rajib Mall. 155-158 [doi]
• Reconsideration of Software Reliability MeasurementsShiyi Xu. 159-164 [doi]
• An Accurate Analysis of Microprocessor Design VerificationHaihua Shen, Heng Zhang. 165-171 [doi]
• Optimized Assignment Coverage Computation in Formal Verification of Digital SystemsMajid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi. 172-177 [doi]
• EHSAT Modeling from Algorithm Description for RTL Model CheckingXiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao. 178-186 [doi]
• Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-ChipThomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara. 187-192 [doi]
• Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoCJaehoon Song, Juhee Han, Dooyoung Kim, Hyunbean Yi, Sungju Park. 193-198 [doi]
• Test Scheduling for Memory Cores with Built-In Self-RepairTomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara. 199-206 [doi]
• Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All SidesYasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian. 207 [doi]
• IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test StrategyYu Wei P'ng, Moo Kit Lee, Peng Weng Ng, Chin Hu Ong. 211 [doi]
• Experimental Results of Transition Fault Simulation with DC Scan TestsWataru Kawamura, Takeshi Onodera. 212 [doi]
• A Review of Power Strategies for DFT and ATPGBrion L. Keller, Tom Jackson, Anis Uzzaman. 213 [doi]
• Concurrent Test ImplementationsShawn Molavi, Toby McPheeters. 214 [doi]
• Scan Diagnosis and Its Successful Industrial ApplicationsWu Yang, Wu-Tung Cheng, Yu Huang 0005, Martin Keim, Randy Klingenberg. 215 [doi]
• A 2-ps Resolution Wide Range BIST Circuit for Jitter MeasurementNai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen. 219-223 [doi]
• An Accurate Jitter Estimation Technique for Efficient High Speed I/O TestingDongwoo Hong, Kwang-Ting Cheng. 224-229 [doi]
• Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform MethodsXinsong Zhang, Simon S. Ang, Chandra Carter. 230-238 [doi]
• Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS CircuitsFlorence Azaïs, Laurent Larguier, Michel Renovell. 239-244 [doi]
• Effect of IR-Drop on Path Delay Testing Using Statistical AnalysisChunsheng Liu, Yang Wu, Yu Huang 0005. 245-250 [doi]
• Low Power Reduced Pin Count Test MethodologyKrishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane. 251-258 [doi]
• Test Generation for Crosstalk Glitches Considering Multiple Coupling EffectsMinjin Zhang, Xiaowei Li 0001. 259-264 [doi]
• Simulating Open-Via DefectsStefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker 0001. 265-270 [doi]
• Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test GeneratorYoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu. 271-274 [doi]
• Fault-dependent/independent Test Generation Methods for State Observable FSMsToshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara. 275-280 [doi]
• Improving Performance of Effect-Cause Diagnosis with Minimal Memory OverheadHuaxing Tang, Chen Liu, Wu-Tung Cheng, Sudahkar M. Reddy, Wei Zou. 281-287 [doi]
• An Efficient Diagnostic Test Pattern Generation Framework Using Boolean SatisfiabilityFeijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna. 288-294 [doi]
• Programmable Logic BIST for At-speed TestYu Huang 0005, Xijiang Lin. 295-300 [doi]
• Diagnostic Test Generation Targeting Equivalence ClassesIrith Pomeranz, Sudhakar M. Reddy. 301-306 [doi]
• Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential ElementsMingjing Chen, Alex Orailoglu. 307-312 [doi]
• CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar ProcessorsShijian Zhang, Weiwu Hu. 313-318 [doi]
• Monitoring Transient Errors in Sequential CircuitsRamashis Das, John P. Hayes. 319-322 [doi]
• Frequency Analysis Method for Propagation of Transient Errors in Combinational LogicShaohua Lei, Yinhe Han, Xiaowei Li. 323-328 [doi]
• Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware CostDong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara. 329-334 [doi]
• Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced ScanGefu Xu, Adit D. Singh. 335-340 [doi]
• An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed TestingXiaoxin Fan, Yu Hu 0001, Laung-Terng Wang. 341-348 [doi]
• A Hybrid BIST Scheme for Multiple Heterogeneous Embedded MemoriesLi-Ming Denq, Cheng-Wen Wu. 349-354 [doi]
• CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMsHsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu. 355-360 [doi]
• Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2)Jochen Rivoir. 361-366 [doi]
• Test Roles in Diagnosis and Silicon DebugAnis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera. 367 [doi]
• Programmable Scan-Based Logic Built-In Self TestLiyang Lai, Wu-Tung Cheng, Thomas Rinderknecht. 371-377 [doi]
• Evaluation of a BIST Technique for CMOS ImagersLivier Lizarraga, Salvador Mir, Gilles Sicard. 378-383 [doi]
• Built-In Speed Grading with a Process-Tolerant ADPLLHsuan-Jung Hsu, Chun-Chieh Tu, Shi-Yu Huang. 384-392 [doi]
• Testing RF Components with Supply Current SignaturesSelim Sermet Akbay, Shreyas Sen, Abhijit Chatterjee. 393-398 [doi]
• Current Testable Design of Resistor String DACsMasaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura. 399-403 [doi]
• Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal ICLiquan Fang, Yang Zhong, H. van de Donk, Yizi Xing. 404-412 [doi]
• Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling InputsNan-Cheng Lai, Sying-Jyan Wang. 413-418 [doi]
• Scan Power Reduction Through Scan Architecture Modification And Test Vector ReorderingChandan Giri, Pradeep Kumar Choudhary, Santanu Chattopadhyay. 419-424 [doi]
• Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction TechniqueBo-Hua Chen, Wei-Chung Kao, Bing-Chuan Bai, Shyue-Tsong Shen, James C.-M. Li. 425-432 [doi]
• SUPERB: Simulator Utilizing Parallel Evaluation of Resistive BridgesPiet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker 0001. 433-438 [doi]
• Symbolic Path Sensitization Analysis and ApplicationsJian Kang, Sharad C. Seth, Shashank K. Mehta. 439-444 [doi]
• Improving Test Pattern Compactness in SAT-based ATPGStephan Eggersglüß, Rolf Drechsler. 445-452 [doi]
• An HDL-Based Platform for High Level NoC Switch TestingMahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi. 453-458 [doi]
• Area Overhead and Test Time Co-Optimization through NoC Bandwidth SharingFawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara. 459-462 [doi]
• Test Efficiency Analysis and Improvement of SOC Test PlatformsTong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You. 463-466 [doi]
• Block Marking and Updating Coding in Test Data Compression for SoCLei Zhang, Huaguo Liang, Wenfa Zhan, Cuiyun Jiang. 467-472 [doi]
• Issues Regarding New Product Release in Semiconductor ManufacturingChoon-Sang Chew. 473 [doi]
• How the noise floor affects the production yieldAkinori Maeda. 474 [doi]
• Integrated Test Solution for embedded UHF/RF SOCSean Lu, Dee-Won Lee. 475 [doi]
• Production Test of High Volume Commercial RFICFriedrich Taenzler. 476 [doi]
• Enhanced Broadside Testing for Improved Transition Fault CoverageIrith Pomeranz, Sudhakar M. Reddy. 479-484 [doi]
• On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing AnalysisI-De Huang, Sandeep K. Gupta. 485-492 [doi]
• Test Generation for Timing-Critical Transition FaultsXijiang Lin, Mark Kassab, Janusz Rajski. 493-500 [doi]
• Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric CellsJin-Fu Li. 501-506 [doi]
• Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell BehaviorMagali Bastian, Vincent Gouin, Patrick Girard 0001, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel. 507-510 [doi]
• Using FPGA configuration memory to accelerate yield learning for advanced processJenny Fan, Xiao Yu Li, Ismed Hartanto. 511-516 [doi]
• Bluetooth Hopping BER Testing Methodologies on a Production Test PlatformDavid Bement, David Karr. 517 [doi]
• Understanding GSM/EDGE Modulated Signal Test on Cellular BB SOCDeng Yue. 518 [doi]
• Top 5 Issues in Practical Testing of High-Speed Interface DevicesTakahiro J. Yamaguchi. 519 [doi]
• Special Session: Analog Production TestFidel Muradali, Jochen Rivoir. 523 [doi]