Srinivas Patil - researchr alias

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Viewing Publication 1 - 31 from 31

2012

Functional Test-Sequence Grading at Register-Transfer LevelHongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti. tvlsi, 20(10):1890-1894, 2012. [doi]

Test generation for clock-domain crossing faults in integrated circuitsNaghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil. date 2012: 406-411 [doi]

2011

Testing of Clock-Domain Crossing Faults in Multi-core System-on-ChipNaghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil. ats 2011: 7-14 [doi]

2009

2008

A low-cost concurrent error detection technique for processor control logicRamtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche. date 2008: 897-902 [doi]

2007

Analysis of Specified Bit Handling Capability of Combinational Expander NetworksAbhijit Jas, Srinivas Patil. dft 2007: 252-260 [doi]

The Region-Exhaustive Fault ModelAbhijit Jas, Suriyaprakash Natarajan, Srinivas Patil. ats 2007: 13-18 [doi]

Estimating the Fault Coverage of Functional Test Sequences Without Fault SimulationIrith Pomeranz, Praveen Parvathala, Srinivas Patil. ats 2007: 25-32 [doi]

2006

2005

Compressing Functional Tests for MicroprocessorsKedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil. ats 2005: 428-433 [doi]

1996

A weighted random pattern test generation systemRohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams. tcad, 15(8):1020-1025, 1996. [doi]

1994

Design of an Efficient Weighted-Random-Pattern Generation SystemRohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams. itc 1994: 491-500

On broad-side delay testJacob Savir, Srinivas Patil. vts 1994: 284-290 [doi]

On broad-side delay testJacob Savir, Srinivas Patil. tvlsi, 2(3):368-372, 1994. [doi]

Broad-side delay testJacob Savir, Srinivas Patil. tcad, 13(8):1057-1064, 1994. [doi]

1993

Scan-based transition testJacob Savir, Srinivas Patil. tcad, 12(8):1232-1241, 1993. [doi]

1992

Skewed-Load Transition Test: Part 2, CoverageSrinivas Patil, Jacob Savir. itc 1992: 714-722

1991

A Layout Driven Design for Testability Technique for MOS VLSI CircuitsSungho Kim, Prithviraj Banerjee, Srinivas Patil. itc 1991: 157-165

Parallel Test Generation for Sequential Circuits on General-Purpose MultiprocessorsSrinivas Patil, Prithviraj Banerjee, Janak H. Patel. dac 1991: 155-159 [doi]

Performance trade-offs in a parallel test generation/fault simulation environmentSrinivas Patil, Prithviraj Banerjee. tcad, 10(12):1542-1558, 1991. [doi]

Parallel algorithms for test generation and fault simulationSrinivas Patil. PhD thesis, University of Illinois Urbana-Champaign, USA, 1991. [doi]

1990

A parallel branch and bound algorithm for test generationSrinivas Patil, Prithviraj Banerjee. tcad, 9(3):313-322, 1990. [doi]

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2012

2011

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1996

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1989

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