Table of Contents

• An integrated floating point vector processor for DSP and scientific computingD. Spaderna, P. Green, K. Tam, T. Datta, M. Kumar. 8-13 [doi]
• FPC: a floating-point processor controller chip for systolic signal processingRoss A. W. Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken. 14-17 [doi]
• A fast algorithm for mixed-radix conversion in residue arithmeticÇetin Kaya Koç. 18-21 [doi]
• SLAM: a smart analog module layout generator for mixed analog-digital VLSI designDavid J. Chen, Ji-chien Lee, Bing J. Sheu. 24-27 [doi]
• Schematic specification of datapath layoutDonald Curry. 28-34 [doi]
• A channelless layout for multilevel synthesis with compiled cellsGabriele Saucier, Régis Leveugle, Pierre Abouzeid. 35-38 [doi]
• A test generation system for path delay faultsSrinivas Patil, Sudhakar M. Reddy. 40-43 [doi]
• A framework for evaluating test pattern generation strategiesTracy Larrabee. 44-47 [doi]
• Intelligent backtracking in test generation for combinational circuitsW. B. Zeng, D. Z. Wei. 48-51 [doi]
• Integrated optoelectronics-to-VLSI packaging technologyC. G. Lin-Hendel, W. J. Bertram, M. S. Dhanaliwala, R. J. Pimpinella, J. M. Segelken, K. L. Tai. 54-57 [doi]
• Optical interconnects for interprocessor communications in the Connection MachineBrewster O. Kahle, Edward C. Parish, Thomas A. Lane, Jerry A. Quam. 58-61 [doi]
• An integrated free space optical busAlex G. Dickinson, Michael E. Prise. 62-65 [doi]
• A low-impedance load detector circuit for optical interconnectsYang-Tung Huang, Raymond K. Kostuk. 66-71 [doi]
• A general-purpose video signal processor: architecture and programmingH. Dijkstra, G. Essink, A. J. M. Hafkamp, H. den Hengst, C. M. Huizer, Arthur H. M. van Roermund, Robert J. Sluyter, P. J. Snijder. 74-77 [doi]
• Motion estimation VLSI architecture for image codingGilles Privat, Marc Renaudin. 78-81 [doi]
• Generic ASIC architecture for digital signal processingStewart G. Smith, Ralph W. Morgan, Julian G. Payne. 82-85 [doi]
• The matrix transform chipSailesh K. Rao. 86-89 [doi]
• A global floorplanning technique for VLSI layoutAlexander Herrigel, M. Glaser, Wolfgang Fichtner. 92-95 [doi]
• A fast floor planning algorithm for architectural evaluationMichael C. McFarland. 96-99 [doi]
• Accurate prediction of physical design characteristics for random logicMassoud Pedram, Bryan Preas. 100-108 [doi]
• Floorplan optimization on multiprocessorsSunil Arvindam, Vipin Kumar, V. Nageshwara Rao. 109-114 [doi]
• Design of TSC checkers for implementation in CMOS technologySandip Kundu, Sudhakar M. Reddy. 116-119 [doi]
• Design of sufficiently strongly self-checking embedded checkers for systematic and separable codesNiraj K. Jha. 120-123 [doi]
• Concurrent checking in dedicated controllersRégis Leveugle, Gabriele Saucier. 124-127 [doi]
• Computation with simultaneously concurrent error detection using bi-directional operandsL.-G. Chen, T. H. Chen. 128-131 [doi]
• An IBM second generation RISC processor architectureRandy D. Groves, Richard R. Oehler. 134-137 [doi]
• IBM second-generation RISC machine organizationH. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan. 138-142 [doi]
• IBM RISC chip design methodologyPaul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel. 143-147 [doi]
• A novel message switch for highly parallel systemsShiwei Wang, Yarsun Hsu, C. J. Tan. 150-155 [doi]
• An algorithm for voice and data integration on packet-switched local area networksChristopher Bucci, Alexander Albicki. 156-159 [doi]
• A microprogrammable VLSI routing controller for HARTSJames W. Dolter, Parmesh Ramanathan, Kang G. Shin. 160-163 [doi]
• Efficient double asymmetric error correcting codesNasir Darwish, Bella Bose. 166-171 [doi]
• High throughput reconstruction of Huffman-coded imagesHorng-Dar Lin, David G. Messerschmitt. 172-175 [doi]
• Fault-tolerant VLSI processor array for the SVDJoseph R. Cavallaro, Christopher D. Near, M. Ümit Uyar. 176-180 [doi]
• Performance and microarchitecture of the i486TM processorBeatrice Fu, Avtar Saini, Patrick P. Gelsinger. 182-187 [doi]
• High performance circuits for the i486TM processorJames Miller, Ben Roberts, Paul Madland. 188-192 [doi]
• Issues in the implementation of the i486TM cache and busEd Grochowski, Ken Shoemaker. 193-198 [doi]
• Computer aided design and built in self test on the i486TM CPUPatrick Gelsinger, Sundar Iyengar, Joseph Krauskopf, James Nadir. 199-202 [doi]
• Formal verification of state-machines using higher-order logicPaul Loewenstein. 204-207 [doi]
• Modeling timing assumptions with trace theoryJerry R. Burch. 208-211 [doi]
• Automatic verification of speed-independent circuits with Petri net specificationsDavid L. Dill, Steven M. Nowick, Robert F. Sproull. 212-216 [doi]
• Verifying pipelined hardware using symbolic logic simulationSoumitra Bose, Allan L. Fisher. 217-221 [doi]
• The design of a multi-chip single package digital signal processing moduleC. G. Lin-Hendel, L. H. Cong. 224-228 [doi]
• Integration and packaging plateaus of processor performanceNorman P. Jouppi. 229-232 [doi]
• Comparison of chip crossing delay in various packaging environmentsRavi Kaw. 233-236 [doi]
• Computer aided design system for VLSI interconnectionsJerzy W. Rozenblit, John L. Prince, Olgierd A. Palusinski, T. D. Whipple. 237-241 [doi]
• An automatic test pattern generation program for large ASICsDick L. Liu, Rajesh Galivanche, Charlie C. Hsu. 244-248 [doi]
• The role of synthesis in an ASIC design environmentJeffrey R. Fox, Douglas Pastorello. 249-254 [doi]
• Evolution in the application of ASICs in the second-generation TitanGlen S. Miranker, Jon Rubinstein, John Sanguinetti. 255-259 [doi]
• Multiple-valued Boolean minimization based on graph coloringMaciej J. Ciesielski, Saeyang Yang, Marek A. Perkowski. 262-265 [doi]
• Correctness verification of VLSI modules supported by a very efficient Boolean proverP. Lammens, Luc J. M. Claesen, Hugo De Man. 266-269 [doi]
• OPAM: an efficient output phase assignment for multilevel logic minimizationChin-Long Wey, Sin-Min Chang, Jing-Yang Jou. 270-273 [doi]
• Fast MOS circuit simulation with a direct equation solverY.-H. Shih, S. M. Kang. 276-279 [doi]
• Frigg: a simulation environment for multiple-processor DSP system developmentJeffrey C. Bier, Edward A. Lee. 280-283 [doi]
• Magnitude classes in switch-level modelingEduard Cerny, John P. Hayes, Nicholas C. Rumin. 284-288 [doi]
• Identification of undetectable faults in combinational circuitsMohan Harihara, Prem R. Menon. 290-293 [doi]
• An enhanced high performance combinational fault simulator using two-way parallelismSteven P. Smith. 294-297 [doi]
• Parallel-concurrent fault simulationDaniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh. 298-301 [doi]
• BiCMOS, a technology for high-speed/high-density ICsH. Klose, B. Zehner, A. Wieder. 304-309 [doi]
• Impact of BiCMOS technology on SRAM circuit designP. Kuen Fung, Hiep V. Tran, David B. Scott. 310-313 [doi]
• Internal ECL-BiCMOS translator circuits in half micron technologyGerard Boudon, Frank Wallart, Eric Maillart. 314-317 [doi]
• Circuit technologies for BiCMOS VLSI's as computer elementsHideo Maejima, Tadaaki Bandoh, Yoji Nishio, Tadashi Fukushima, Masanori Odaka, Atsuo Hotta. 318-321 [doi]
• A logic network synthesis system, SYLONS. Muroga, X. Q. Xiang, J. Limqueco, L. P. Lin, K.-C. Chen. 324-328 [doi]
• Logic decomposition algorithms for the timing optimization of multi-level logicPierre G. Paulin, Franck J. Poirot. 329-333 [doi]
• Automated synthesis of systems with interacting asynchronous (self-timed) and synchronous componentsP. A. Subrahmanyam. 334-337 [doi]
• Testability of digital circuits via the spectral domainBrian R. Bannister, David R. Melton, Gaynor E. Taylor. 340-343 [doi]
• Hamming count-a compaction testing techniqueAnita Gleason, Wen-Ben Jone. 344-347 [doi]
• A VLSI residue arithmetic multiplier with fault detection capabilityV. Bobin, D. Radhakrishnan. 348-351 [doi]
• Improved testability evaluations in combinational logic networksSilvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò. 352-355 [doi]
• A high performance BiCMOS 32-bit microprocessorYasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto. 358-361 [doi]
• Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systemsNobuhiro Tomabechi. 362-365 [doi]
• A VLSI module for IEEE floating-point multiplication/division/square rootPaul Y. Lu, Kevin Dawallu. 366-368 [doi]
• Adaptive and pipelined VLSI designs for tree-based codesAmar Mukherjee, N. Ranganathan, Mostafa A. Bassiouni. 369-372 [doi]
• An 80 MFLOPS floating-point engine in the Intel i860(TM) processorHon P. Sit, Monica Rosenrauch Nofal, Sunhyuk Kimn. 374-379 [doi]
• The bus interface and paging units of the i860TM microprocessorMichael W. Rhodehamel. 380-384 [doi]
• Architectural features of the i860(TM)-microprocessor RISC core and on-chip cachesPiyush Patel, Diane Douglass. 385-390 [doi]
• Ordered binary decision diagrams and circuit structureC. Leonard Berman. 392-395 [doi]
• Logic minimization for factored formsAbdul A. Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 396-399 [doi]
• A generalized approach to the constrained cubical embedding problemBill Lin, A. Richard Newton. 400-403 [doi]
• A 32-bit microprocessor with high performance bit-map manipulation instructionsToru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito. 406-409 [doi]
• Novel architecture for a high performance full custom graphics processorM. D. Asal, J. D. Keay, A. M. Fellows, I. C. Robertson, N. K. Ing-Simmons, I. J. Sherlock. 410-414 [doi]
• High performance I/O processors for real-time pulse handlingMasayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago. 415-418 [doi]
• Mind: a module binder for high level synthesisChia-Jeng Tseng, Steven G. Rothweiler, Shailesh Sutarwala, Ajit M. Prabhu. 420-423 [doi]
• A cost function based optimization technique for scheduling in data path synthesisHyunchul Shin, Nam Sung Woo. 424-427 [doi]
• DAGAR: an automatic pipelined microarchitecture synthesis systemVijay K. Raj. 428-431 [doi]
• HYPER: an interactive synthesis environment for high performance real time applicationsChi-Min Chu, Miodrag Potkonjak, Markus Thaler, Jan M. Rabaey. 432-435 [doi]
• Reliability issues of MOS and bipolar ICsChenming Hu. 438-442 [doi]
• A yield model for the evaluation of topologically constrained chip architecturesBruno Ciciani, Giuseppe Iazeolla. 443-446 [doi]
• Electromigration median time-to-failure based on a stochastic current waveformFarid N. Najm, Ibrahim N. Hajj, Ping Yang 0001. 447-450 [doi]
• On a class of (2n-1)-stage rearrangeable interconnection networksCalvin J. A. Hsia, C. Y. Roger Chen. 452-455 [doi]
• A systolic approach to multistage interconnection network designChung-Han Chen, Laxmi N. Bhuyan. 456-459 [doi]
• Systolic L-U decomposition array with a new reciprocal cellVijay K. Jain, David L. Landis, C. E. Alvarez. 460-465 [doi]
• The design and implementation of a multi-queue buffer for VLSI communication switchesGregory L. Frazier, Yuval Tamir. 466-471 [doi]
• A fuzzy logic controller with reconfigurable, cascadable architectureWayne D. Dettloff, Kathy E. Yount, Hiroyuki Watanabe. 474-478 [doi]
• Systolic implementation of neural networksM. Zubair, B. B. Madan. 479-482 [doi]
• A flexible architecture for neural networksJ. Ouali, Gabriele Saucier. 483-486 [doi]
• Issues in the test of artificial neural networksFrank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg. 487-490 [doi]
• Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliabilityYusuf Leblebici, Sung-Mo Kang. 492-495 [doi]
• Digital and analog integrated-circuit design with built-in reliabilityWen-Jay Hsu, Bing J. Sheu, Vance C. Tyree. 496-499 [doi]
• A module-sliced approach for high yield VLSI/WSI processorsYi-Chieh Chang, Kang G. Shin. 500-503 [doi]
• Locality characteristics of symbolic programsWilliam C. Hobart Jr., Harvey G. Cragon. 508-511 [doi]
• A design of a memory management unit for object-based systemsUmakishore Ramachandran, M. Yousef Amin Khalidi. 512-517 [doi]
• A cached system architecture dedicated for the system IO activity on a CPU boardMichael M. Hsieh, Tek C. Wei, William Van Loo. 518-522 [doi]
• Automatic signal net-matching for VLSI layout designXiao-Ming Xiong, Dan Green, John Hardin, Lawrence Riedel. 524-527 [doi]
• The channel intersection problem in the building block style layoutPierre-François Dubois. 528-531 [doi]
• A hierarchical constraint graph generation and compaction system for symbolic layoutA. A. J. de Lange, J. S. J. de Lange, J. F. Vink. 532-535 [doi]
• Macrocell-level compaction with automatic jog introductionAlexander Herrigel, J. Kamm, Wolfgang Fichtner. 536-539 [doi]
• System-level design verification in the AT&T computer division: overview and strategyMiron Abramovici, J. W. Bierbauer, R. H. Hellman, C. L. Hong, David T. Miller, R. G. Taylor. 542-547 [doi]
• System-level design verification in the AT&T Computer Division: toolsMiron Abramovici, James J. Kulikowski, David T. Miller, Prem R. Menon. 548-554 [doi]
• A system simulation environment within DigitalQuinn Canfield, Paul Barford, Paul Kinzelman, Cary Trlica. 555-560 [doi]
• FOCUS: an experimental environment for validation of fault-tolerant systems - case study of a jet-engine controllerGwan Choi, Ravi K. Iyer, Victor Carreno. 561-564 [doi]
• Scheduling unequal length tests in high performance VLSI system implementationsJohn Y. Sayah, Charles R. Kime. 566-570 [doi]
• Built-in test methodology for a full custom processor chipRavinder S. Shergill, Pak-Ho Yeung, Patrick A. Tucci. 571-575 [doi]
• An efficient approach to pseudo-exhaustive test generation for BIST designChien-In H. Chen, Gerald E. Sobelman. 576-579 [doi]
• Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architectureYervant Zorian, Najmi Jarwala. 580-584 [doi]