Charles R. Moore - researchr alias

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Viewing Publication 1 - 20 from 20

2012

Exploiting microarchitectural redundancy for defect tolerancePremkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger. iccd 2012: 35-42 [doi]

2011

Power efficiency as the #1 design constraint: technical perspectiveCharles R. Moore. CACM, 54(10):84, 2011. [doi]

2008

Microarchitecture in the system-level integration eraCharles R. Moore. euromicro 2008: [doi]

2004

Scaling to the End of Silicon with EDGE ArchitecturesDoug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode. Computer, 37(7):44-55, 2004. [doi]

Managing the Transition from Complexity to Elegance: Design ConvergenceCharles R. Moore. micro, 24(1):80, 2004. [doi]

TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLPKarthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore. taco, 1(1):62-93, 2004. [doi]

Scalable Hardware Memory Disambiguation for High-ILP ProcessorsSimha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler. micro, 24(6):118-127, 2004. [doi]

2003

Managing the Transition from Complexity to Elegance: Knowing When You Have a ProblemCharles R. Moore. micro, 23(5), 2003. [doi]

Guest Editors Introduction: Micro s Top Picks from Microarchitecture ConferencesCharles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose. micro, 23(6):8-10, 2003. [doi]

Microprocessor pipeline energy analysisKarthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger. islped 2003: 282-287 [doi]

Exploiting ILP, TLP and DLP with the Polymorphous TRIPS ArchitectureKarthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore. isca 2003: 422-433 [doi]

Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS ArchitectureKarthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore. micro, 23(6):46-51, 2003. [doi]

Scalable Hardware Memory Disambiguation for High ILP ProcessorsSimha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler. euromicro 2003: 399-410 [doi]

Exploiting Microarchitectural Redundancy For Defect TolerancePremkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger. iccd 2003: 481-488 [doi]

1994

The PowerPC AllianceCharles R. Moore, Russell C. Stanphill. CACM, 37(6):25-27, 1994.

Design considerations for the PowerPC 601 microprocessorMichael T. Vaden, Lawrence J. Merkel, Charles R. Moore, Terence M. Potter, Robert James Reese. ibmrd, 38(5):605-620, 1994.

1993

The Power PC 601 microprocessorMichael C. Becker, Michael S. Allen, Charles R. Moore, John S. Muhich, David P. Tuttle. micro, 13(5):54-68, 1993. [doi]

1992

IBM Single Chip RISC Processor (RSC)Charles R. Moore, D. M. Balser, J. S. Muhich, R. E. East. iccd 1992: 200-204

1989

IBM second-generation RISC machine organizationH. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan. iccd 1989: 138-142 [doi]

1974

Character string manipulation in APLCharles R. Moore. apl 1974: 349-353 [doi]

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