Abstract is missing.
- Microarchitecture on the MOSFET DietKerry Bernstein. 3-6 [doi]
- VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low PowerHai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy. 19-28 [doi]
- A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance MicroprocessorShubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin. 29-42 [doi]
- TLC: Transmission Line CachesBradford M. Beckmann, David A. Wood. 43-54 [doi]
- Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache ArchitecturesZeshan Chishti, Michael D. Powell, T. N. Vijaykumar. 55-66 [doi]
- Near-Optimal Precharging in High-Performance Nanoscale CMOS CachesSe-Hyun Yang, Babak Falsafi. 67-80 [doi]
- Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power ReductionRakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen. 81-92 [doi]
- Runtime Power Monitoring in High-End Processors: Methodology and Empirical DataCanturk Isci, Margaret Martonosi. 93-104 [doi]
- Power-driven Design of Router Microarchitectures in On-chip NetworksHangsheng Wang, Li-Shiuan Peh, Sharad Malik. 105-116 [doi]
- Optimum Power/Performance Pipeline DepthAllan Hartstein, Thomas R. Puzak. 117-128 [doi]
- Processor Acceleration Through Automated Instruction Set CustomizationNathan Clark, Hongtao Zhong, Scott A. Mahlke. 129-140 [doi]
- The Reconfigurable Streaming Vector Processor (RSVPTM)Silviu Ciricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael A. Schuette, Ali Saidi. 141-150 [doi]
- Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and PracticeRichard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen. 151-164 [doi]
- In Memory of Bob RauMichael S. Schlansker. 165-168 [doi]
- Generational Cache Management of Code Traces in Dynamic Optimization SystemsKim M. Hazelwood, Michael D. Smith. 169-179 [doi]
- The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization SystemJiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen. 180-190 [doi]
- IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systemsLeonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach. 191-204 [doi]
- LLVA: A Low-level Virtual Instruction Set ArchitectureVikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke. 205-216 [doi]
- Comparing Program Phase Detection TechniquesAshutosh S. Dhodapkar, James E. Smith. 217-227 [doi]
- Using Interaction Costs for Microarchitectural Bottleneck AnalysisBrian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn. 228-242 [doi]
- Fast Path-Based Neural Branch PredictionDaniel A. Jiménez. 243-252 [doi]
- Hardware Support for Control Transfers in Code CachesHo-Seop Kim, James E. Smith. 253-264 [doi]
- Exploiting Value Locality in Physical Register FilesSaisanthosh Balakrishnan, Gurindar S. Sohi. 265-276 [doi]
- Macro-op Scheduling: Relaxing Scheduling Loop ConstraintsIlhyun Kim, Mikko H. Lipasti. 277-290 [doi]
- WaveScalarSteven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin. 291-302 [doi]
- Universal Mechanisms for Data-Parallel ArchitecturesKarthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger. 303-314 [doi]
- Flexible Compiler-Managed L0 Buffers for Clustered VLIW ProcessorsEnric Gibert, F. Jesús Sánchez, Antonio González. 315-325 [doi]
- Instruction Replication for Clustered MicroarchitecturesAlex Aletà, Josep M. Codina, Antonio González, David R. Kaeli. 326-338 [doi]
- Efficient Memory Integrity Verification and Encryption for Secure ProcessorsG. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas. 339-350 [doi]
- Fast Secure Processor for Inhibiting Software Piracy and TamperingJun Yang, Youtao Zhang, Lan Gao. 351-360 [doi]
- IPStash: a Power-Efficient Memory Architecture for IP-lookupStefanos Kaxiras, Georgios Keramidas. 361-372 [doi]
- Design and Implementation of High-Performance Memory Systems for Future Packet BuffersJorge García, Jesús Corbal, Llorenç Cerdà, Mateo Valero. 373-386 [doi]
- Beating in-order stalls with flea-flicker two-pass pipeliningRonald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu. 387-398 [doi]
- Scalable Hardware Memory Disambiguation for High ILP ProcessorsSimha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler. 399-410 [doi]
- Reducing Design Complexity of the Load/Store QueueIl Park, Chong-liang Ooi, T. N. Vijaykumar. 411-422 [doi]
- Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window ProcessorsHaitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan. 423 [doi]