Table of Contents

• Advanced EDA Tools for High-Performance DesignTed Vucurevich. [doi]
• Terascale Computing and BlueGeneWilliam R. Pulleyblank. [doi]
• High-Speed Link Design, Then and NowMark Horowitz. [doi]
• Energy Efficient Asymmetrically Ported Register FilesAneesh Aggarwal, Manoj Franklin. 2-7 [doi]
• Power Efficient Data Cache DesignsJaume Abella, Antonio González. 8-13 [doi]
• On Reducing Register Pressure and Energy in Multiple-Banked Register FilesJaume Abella, Antonio González. 14-20 [doi]
• Low Power Multiplication Algorithm for Switching Activity Reduction through Operand DecompositionMasayuki Ito, David G. Chinnery, Kurt Keutzer. 21 [doi]
• Verification of Timed Circuits with Failure Directed AbstractionsHao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda. 28-35 [doi]
• Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential CircuitsGang Chen, Sudhakar M. Reddy, Irith Pomeranz. 36-41 [doi]
• Event-Centric Simulation of Crosstalk Pulse Faults in Sequential CircuitsMarong Phadoongsidhi, Kewal K. Saluja. 42-47 [doi]
• Specifying and Verifying Systems with Multiple ClocksEdmund M. Clarke, Daniel Kroening, Karen Yorav. 48 [doi]
• Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered DielectricsWenjian Yu, Zeyi Wang, Xianlong Hong. 58-63 [doi]
• An Improved method for Fast Noise Estimation based on Net SegmentationChih-Liang Huang, Aurobindo Dasgupta. 64-79 [doi]
• Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage CurrentHui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein. 70-75 [doi]
• An Efficient Algorithm for Calculating the Worst-case Delay due to CrosstalkVenkatesan Rajappan, Sachin S. Sapatnekar. 76 [doi]
• A Compact Model for Analysis and Design of On-chip Power Network with Decoupling CapacitorsPayman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe. 84-89 [doi]
• Precomputation-based Guarding for Dynamic and Leakage Power ReductionAfshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh. 90-97 [doi]
• Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS CircuitsSaravanan Rajapandian, Zheng Xu, Kenneth L. Shepard. 98-102 [doi]
• Low Power Adder with Adaptive Supply VoltageHiroaki Suzuki, Woopyo Jeong, Kaushik Roy. 103-106 [doi]
• A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register FileNestoras Tzartzanis, William W. Walker. 107 [doi]
• Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated DevicesRastislav Levicky. 112 [doi]
• Design Flow Enhancements for DNA ArraysAndrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky. 116 [doi]
• Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on ChipNattawut Thepayasuwan, Vaishali Damle, Alex Doboli. 126-133 [doi]
• Dynamically Optimized Synchronous Communication for Low Power System on Chip DesignsVikas Chandra, Gary D. Carpenter, Jeffrey L. Burns. 134-139 [doi]
• Interface Synthesis using Memory Mapping for an FPGA PlatformManev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. 140-145 [doi]
• Efficient Synthesis of Networks On ChipAlessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 146-150 [doi]
• Reducing Compilation Time Overhead in Compiled SimulatorsMehrdad Reshadi, Nikil D. Dutt. 151 [doi]
• Profiling Interrupt Handler Performance through Kernel InstrumentationBranden J. Moore, Thomas Slabach, Lambert Schaelicke. 156-163 [doi]
• Design and Performance of Compressed Interconnects for High Performance ServersKrishna Kant, Ravishankar K. Iyer. 164-169 [doi]
• Routed Inter-ALU Networks for ILP Scalability and PerformanceKarthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger. 170 [doi]
• Automatic Generation of Critical-Path Tests for a Partial-Scan MicroprocessorJoel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies. 180-186 [doi]
• Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based ApproachLoganathan Lingappan, Srivaths Ravi, Niraj K. Jha. 187-193 [doi]
• Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction CaseSobeeh Almukhaizim, Thomas Verdel, Yiorgos Makris. 194-197 [doi]
• Multiple Fault Diagnosis Using n-Detection TestsZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. 198 [doi]
• A Physical Design Methodology for 1.3GHz SPARC64 MicroprocessorNoriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura. 204-210 [doi]
• Physical Design of the 2.5D Stacked SystemYangdong Deng, Wojciech Maly. 211-217 [doi]
• Flow-Based Cell Moving Algorithm for Desired Cell DistributionBo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh. 218 [doi]
• NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network ProcessorsByeong Kil Lee, Lizy Kurian John. 226-233 [doi]
• Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost AnalysisNihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan. 234-239 [doi]
• Pipelined Multiplicative Division with IEEE RoundingGuy Even, Peter-Michael Seidel. 240 [doi]
• Design of Resonant Global Clock DistributionsSteven C. Chan, Kenneth L. Shepard, Phillip Restle. 248-253 [doi]
• Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O LinksGanesh Balamurugan, Naresh R. Shanbhag. 254-260 [doi]
• A Mixed-Mode Delay-Locked-Loop ArchitectureDaniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors. 261-263 [doi]
• Optimal Inductance for On-chip RLC InterconnectionsShidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester. 264 [doi]
• Spec Based Flip-Flop And Buffer InsertionNataraj Akkiraju, Mosur Mohan. 270-275 [doi]
• A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power OptimizationN. Ranganathan, Ashok K. Murugavel. 276-281 [doi]
• A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock RoutingRishi Chaturvedi, Jiang Hu. 282 [doi]
• Hardware-based Pointer Data PrefetcherShih-Chang Lai, Shih-Lien Lu. 290-298 [doi]
• A Dependence Driven Efficient Dispatch SchemeSriram Nadathur, Akhilesh Tyagi. 299-306 [doi]
• An Efficient VLIW DSP Architecture for Baseband ProcessingTay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen. 307-312 [doi]
• Dynamic Thread Resizing for Speculative Multithreaded ProcessorsMohamed M. Zahran, Manoj Franklin. 313 [doi]
• Care Bit Density and Test Cube Clusters: Multi-Level Compression OpportunitiesBernd Könemann. 320 [doi]
• XMAX: X-Tolerant Architecture for MAXimal Test CompressionSubhasish Mitra, Kee Sup Kim. 326-330 [doi]
• Test Data Compression and Compaction for Embedded Test of Nanometer Technology DesignsJanusz Rajski, Jerzy Tyszer. 331 [doi]
• Non-Crossing OBDDs for Mapping to Regular Circuit StructuresAiqun Cao, Cheng-Kok Koh. 338-343 [doi]
• Interconnect Estimation for FPGAs under Timing Driven DomainsPariVallal Kannan, Dinesh Bhatia. 344-349 [doi]
• ROAD : An Order-Impervious Optimal Detailed Router for FPGAsHasan Arslan, Shantanu Dutt. 350 [doi]
• Reducing dTLB Energy Through Dynamic ResizingVictor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan. 358-363 [doi]
• Distributed Reorder Buffer Schemes for Low PowerGurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose. 364-370 [doi]
• Virtual Page Tag Reduction for Low-power TLBsPeter Petrov, Alex Orailoglu. 371-374 [doi]
• Dynamic Cluster ResizingJosé González, Antonio González. 375 [doi]
• Independent Test Sequence Compaction through Integer ProgrammingPetros Drineas, Yiorgos Makris. 380-386 [doi]
• On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data VolumeSeiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty. 387-396 [doi]
• Static Test Compaction for Multiple Full-Scan CircuitsIrith Pomeranz, Sudhakar M. Reddy. 393-396 [doi]
• A Method to Find Don t Care Values in Test Sequences for Sequential CircuitsYoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz. 397 [doi]
• Simplifying SoC design with the Customizable Control Processor PlatformC. Ross Ogilvie, Richard Ray, Robert Devins, Mark Kautzman, Michael Hale, Reinaldo A. Bergamaschi, Bob Lynch, Santosh Gaur. 402-403 [doi]
• Structured ASICs: Opportunities and ChallengesBehrooz Zahiri. 404-409 [doi]
• System LSI Implementation Fabrics for the Future (special panel discussion)Sinan Kaptanoglu. 410 [doi]
• Multiple-Vdd Scheduling/Allocation for Partitioned FloorplanDongku Kang, Mark C. Johnson, Kaushik Roy. 412-418 [doi]
• SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection ArchitectureYoung-Su Kwon, Bong-Il Park, Chong-Min Kyung. 419-425 [doi]
• A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function UnitsKaushal R. Gandhi, Nihar R. Mahapatra. 426 [doi]
• KnapBind: An Area-Efficient Binding Algorithm for Low-leakage DatapathsChandramouli Gopalakrishnan, Srinivas Katkoori. 430-435 [doi]
• A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP CircuitsMadhubanti Mukherjee, Ranga Vemuri. 436-440 [doi]
• Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath SchedulingSaraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi. 441-443 [doi]
• An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc NetworksFarhad Ghasemi-Tari, Peng Rong, Massoud Pedram. 444 [doi]
• CMOS High-Speed I/Os - Present and FutureM.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John Poulton. 454-461 [doi]
• Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar TransistorsK. Kiziloglu, S. Seetharaman, K. W. Glass, C. Bil, H. V. Duong, G. Asmanis. 462-466 [doi]
• Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication SystemsMike P. Li, Jan B. Wilstrup. 467 [doi]
• Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded SystemsChanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim, Bumsoo Kim. 474-480 [doi]
• Exploiting Microarchitectural Redundancy For Defect TolerancePremkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger. 481-488 [doi]
• Reducing Multimedia Decode Power using Feedback ControlZhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron. 489 [doi]
• Structural Detection of Symmetries in Boolean FunctionsGuoqiang Wang, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli. 498-503 [doi]
• Boolean Decomposition Based on Cyclic ChainsElena Dubrova, Maxim Teslenko, Johan Karlsson. 504-509 [doi]
• SAT-Based Algorithms for Logic MinimizationSamir Sapra, Michael Theobald, Edmund M. Clarke. 510 [doi]
• Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber ChannelsAnand Selvarathinam, Euncheol Kim, Gwan Choi. 520-525 [doi]
• Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context SwitchesSudeep Pasricha, Alexander V. Veidenbaum. 526-531 [doi]
• Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register FilesSantithorn Bunchua, D. Scott Wills, Linda M. Wills. 532-535 [doi]
• xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCsMatteo Dall Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini. 536 [doi]
• Aggressive Test Power Reduction Through Test Stimuli TransformationOzgur Sinanoglu, Alex Orailoglu. 542-547 [doi]
• Power-Time Tradeoff in Test Scheduling for SoCsMehrdad Nourani, James Chin. 548-553 [doi]
• Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal IntegrityMohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani. 554 [doi]