Farzan Fallah - researchr alias

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Viewing Publication 1 - 57 from 57

2014

Effective Post-Silicon Validation of System-on-Chips Using Quick Error DetectionDavid Lin, Ted Hong, Yanjing Li, Eswaran S, Sharad Kumar, Farzan Fallah, Nagib Hakim, Donald S. Gardner, Subhasish Mitra. tcad, 33(10):1573-1590, 2014. [doi]

2013

2012

Quick detection of difficult bugs for effective post-silicon validationDavid Lin, Ted Hong, Farzan Fallah, Nagib Hakim, Subhasish Mitra. dac 2012: 561-566 [doi]

2009

Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel LengthsBehnam Amelifard, Farzan Fallah, Massoud Pedram. tcad, 28(4):478-489, 2009. [doi]

Xquasher: a tool for efficient computation of multiple linear expressionsArash Arfaee, Ali Irturk, Nikolay Laptev, Farzan Fallah, Ryan Kastner. dac 2009: 254-257 [doi]

2008

Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox TechnologyBehnam Amelifard, Farzan Fallah, Massoud Pedram. tvlsi, 16(7):851-860, 2008. [doi]

Charge Recycling in Power-Gated CMOS CircuitsEhsan Pakbaznia, Farzan Fallah, Massoud Pedram. tcad, 27(10):1798-1811, 2008. [doi]

2007

A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS DesignAfshin Abdollahi, Farzan Fallah, Massoud Pedram. tvlsi, 15(1):80-89, 2007. [doi]

Algebraic Methods for Optimizing Constant Multiplications in Linear SystemsAnup Hosangadi, Farzan Fallah, Ryan Kastner. vlsisp, 49(1):31-50, 2007. [doi]

Sizing and placement of charge recycling transistors in MTCMOS circuitsEhsan Pakbaznia, Farzan Fallah, Massoud Pedram. iccad 2007: 791-796 [doi]

2006

Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignmentBehnam Amelifard, Farzan Fallah, Massoud Pedram. date 2006: 995-1000 [doi]

Low-power fanout optimization using MTCMOS and multi-Vt techniquesBehnam Amelifard, Farzan Fallah, Massoud Pedram. islped 2006: 334-337 [doi]

Low-leakage SRAM Design with Dual V_t TransistorsBehnam Amelifard, Massoud Pedram, Farzan Fallah. isqed 2006: 729-734 [doi]

Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression EliminationAnup Hosangadi, Farzan Fallah, Ryan Kastner. tcad, 25(10):2012-2022, 2006. [doi]

Optimizing high speed arithmetic circuits using three-term extractionAnup Hosangadi, Farzan Fallah, Ryan Kastner. date 2006: 1294-1299 [doi]

An Energy Characterization Framework for Software-Based Embedded SystemsDonghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah. estimedia 2006: 59-64 [doi]

Charge recycling in MTCMOS circuits: concept and analysisEhsan Pakbaznia, Farzan Fallah, Massoud Pedram. dac 2006: 97-102 [doi]

2005

Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI CircuitsAfshin Abdollahi, Farzan Fallah, Massoud Pedram. isqed 2005: 77-82 [doi]

An effective power mode transition technique in MTCMOS circuitsAfshin Abdollahi, Farzan Fallah, Massoud Pedram. dac 2005: 37-42 [doi]

Low-power fanout optimization using multiple threshold voltage invertersBehnam Amelifard, Farzan Fallah, Massoud Pedram. islped 2005: 95-98 [doi]

Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance AddersBehnam Amelifard, Farzan Fallah, Massoud Pedram. isqed 2005: 148-152 [doi]

Standby and Active Leakage Current Control and Minimization in CMOS VLSI CircuitsFarzan Fallah, Massoud Pedram. ieicet, 88-C(4):509-519, 2005. [doi]

Energy Efficient Hardware Synthesis of Polynomial ExpressionsAnup Hosangadi, Farzan Fallah, Ryan Kastner. vlsid 2005: 653-658 [doi]

Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressionsAnup Hosangadi, Farzan Fallah, Ryan Kastner. aspdac 2005: 523-528 [doi]

A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated ProcessorsTohru Ishihara, Farzan Fallah. date 2005: 358-363 [doi]

A cache-defect-aware code placement algorithm for improving the performance of processorsTohru Ishihara, Farzan Fallah. iccad 2005: 995-1001

A non-uniform cache architecture for low power system designTohru Ishihara, Farzan Fallah. islped 2005: 363-368 [doi]

2004

2003

2002

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI CircuitsAfshin Abdollahi, Farzan Fallah. iwls 2002: 419-424

Runtime mechanisms for leakage current reduction in CMOS VLSI circuits:::1, 2:::Afshin Abdollahi, Massoud Pedram, Farzan Fallah. islped 2002: 213-218 [doi]

A Class of Irredundant Encoding Techniques for Reducing Bus PowerYazdan Aghaghiri, Farzan Fallah, Massoud Pedram. jcsc, 11(5):445-458, 2002. [doi]

ALBORZ: Address Level Bus Power OptimizationYazdan Aghaghiri, Farzan Fallah, Massoud Pedram. isqed 2002: 470 [doi]

Reducing transitions on memory buses using sector-based encoding techniqueYazdan Aghaghiri, Massoud Pedram, Farzan Fallah. islped 2002: 190-195 [doi]

EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address BusesYazdan Aghaghiri, Massoud Pedram, Farzan Fallah. date 2002: 1102 [doi]

Binary Time Frame ExpansionFarzan Fallah. iwls 2002: 314-319

Binary time-frame expansionFarzan Fallah. iccad 2002: 458-464 [doi]

Functional vector generation for sequential HDL models under an observability-based code coverage metricFarzan Fallah, Pranav Ashar, Srinivas Devadas. tvlsi, 10(6):919-923, 2002. [doi]

Accelerated SAT-based Scheduling of Control/Data Flow GraphsSeda Ogrenci Memik, Farzan Fallah. iccd 2002: 395 [doi]

2001

Irredundant address bus encoding for low powerYazdan Aghaghiri, Farzan Fallah, Massoud Pedram. islped 2001: 182-187 [doi]

A New Functional Test Program Generation MethodologyFarzan Fallah, Koichiro Takayama. iccd 2001: 76-81

Observability enhanced coverage analysis of C programs for functional validationFarzan Fallah, Indradeep Ghosh. hldvt 2001: 157-162 [doi]

OCCOM-efficient computation of observability-based code coveragemetrics for functional verificationFarzan Fallah, Srinivas Devadas, Kurt Keutzer. tcad, 20(8):1003-1015, 2001. [doi]

Functional vector generation for HDL models using linearprogramming and Boolean satisfiabilityFarzan Fallah, Srinivas Devadas, Kurt Keutzer. tcad, 20(8):994-1002, 2001. [doi]

A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based CoverageSerdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer. iccd 2001: 82-88

2000

Solving covering problems using LPR-based lower boundsFarzan Fallah, Stan Y. Liao, Srinivas Devadas. tvlsi, 8(1):9-17, 2000. [doi]

1999

Coverage-directed validation of hardware modelsFarzan Fallah. PhD thesis, Massachusetts Institute of Technology, Cambridge, MA, USA, 1999. [doi]

Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement CoverageFarzan Fallah, Pranav Ashar, Srinivas Devadas. dac 1999: 666-671 [doi]

1998

Functional Vector Generation for HDL Models Using Linear Programming and 3-SatisfiabilityFarzan Fallah, Srinivas Devadas, Kurt Keutzer. dac 1998: 528-533 [doi]

OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional VerificationFarzan Fallah, Srinivas Devadas, Kurt Keutzer. dac 1998: 152-157 [doi]

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2014

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1998

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