Abstract is missing.
- Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence EquationsFrançois Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner. 6-16 [doi]
- Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent ConditionalsFrank Hannig, Jürgen Teich. 17-27 [doi]
- CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded SystemsVida Kianzad, Shuvra S. Bhattacharyya. 28-40 [doi]
- Reliability-Aware Co-Synthesis for Embedded SystemsYuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. 41-50 [doi]
- Complex Square Root with Operand PrescalingMilos D. Ercegovac, Jean-Michel Muller. 52-62 [doi]
- Parallel Montgomery MultipliersMoboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase. 63-72 [doi]
- Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP ApplicationsAlexandre F. Tenca, Ajay C. Shantilal, Mohammed H. Sinky. 73-83 [doi]
- Decimal Floating-Point Division Using Newton-Raphson IterationLiang-Kai Wang, Michael J. Schulte. 84-95 [doi]
- A Public-Key Cryptographic Processor for RSA and ECCHans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram. 98-110 [doi]
- Architectural Support for Arithmetic in Optimal Extension FieldsJohann Großschädl, Sandeep S. Kumar, Christof Paar. 111-124 [doi]
- Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite FieldsA. Murat Fiskiran, Ruby B. Lee. 125-136 [doi]
- Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile SystemsJongmyon Kim, D. Scott Wills. 137-149 [doi]
- Binary Multiplication based on Single Electron TunnelingCasper Lageweg, Sorin Cotofana, Stamatis Vassiliadis. 152-166 [doi]
- A Novel Highly Reliable Low-Power Nano Architecture When von Neumann AugmentsValeriu Beiu. 167-177 [doi]
- Register Organization for Enhanced On-Chip ParallelismRama Sangireddy. 180-190 [doi]
- Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic DevicesLjiljana Dilparic, D. K. Arvind. 191-201 [doi]
- Common Subexpression Elimination Involving Multiple Variables for Linear DSP SynthesisAnup Hosangadi, Farzan Fallah, Ryan Kastner. 202-212 [doi]
- Optimizing the Memory Bandwidth with Loop MorphingJosé Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor. 213-223 [doi]
- Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP ApplicationsZili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha. 224-234 [doi]
- A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2:::k:::Alex Fit-Florea, David W. Matula. 236-246 [doi]
- An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2:::n:::)Lo ai A. Tawalbeh, Alexandre F. Tenca. 247-257 [doi]
- Detecting Faults in Four Symmetric Key Block CiphersLuca Breveglieri, Israel Koren, Paolo Maistri. 258-268 [doi]
- A Low-Power Carry Skip Adder with Fast SaturationMichael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis. 269-279 [doi]
- A Hierarchical Classification Scheme to Derive Interprocess Communication in Process NetworksAlexandru Turjan, Bart Kienhuis, Ed F. Deprettere. 282-292 [doi]
- Efficient On-Chip Communications for Data-Flow IPsAntoine Fraboulet, Tanguy Risset. 293-303 [doi]
- Automatic Synthesis of Customized Local Memories for Multicluster Application AcceleratorsManjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke. 304-314 [doi]
- Optimized Data-Reuse in Processor ArraysSebastian Siegel, Renate Merker. 315-325 [doi]
- Hyper-Programmable Architectures for Adaptable Networked SystemsGordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni. 328-338 [doi]
- Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable ComputingMiljan Vuletic, Laura Pozzi, Paolo Ienne. 339-351 [doi]
- Families of FPGA-Based Algorithms for Approximate String MatchingTom Van Court, Martin C. Herbordt. 354-364 [doi]
- Biosequence Similarity Search on the Mercury SystemPraveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster. 365-375 [doi]
- Stride Permutation Networks for Array ProcessorsTuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala. 376-386 [doi]
- A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based SystemsFabien Castanier, Alberto Ferrante, Vincenzo Piuri. 387-397 [doi]
- Design of the QBIC Wearable Computing PlatformOliver Amft, Michael Lauffer, Stijn Ossevoort, Fabrizio Macaluso, Paul Lukowicz, Gerhard Tröster. 398-410 [doi]