Renate Merker - researchr alias

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Viewing Publication 1 - 45 from 45

2011

A Cost Model for Partial Dynamic ReconfigurationMarkus Rullmann, Renate Merker. thipeac, 4:370-390, 2011. [doi]

2010

Design Methods and Tools for Improved Partial Dynamic ReconfigurationMarkus Rullmann, Renate Merker. In Marco Platzner, Jürgen Teich, Norbert Wehn, editors, Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications. pages 161-181, Springer, 2010. [doi]

2009

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAsMarkus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner. fpl 2009: 92-98 [doi]

2008

2007

Massively Parallel Processor Architectures: A Co-design ApproachHritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier. recosoc 2007: 61-68

A Reconfiguration Aware Circuit Mapper for FPGAsMarkus Rullmann, Renate Merker. ipps 2007: 1-8 [doi]

2006

An Architecture Description Language for Massively Parallel Processor ArchitecturesAlexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker. mbmv 2006: 11-20

Maximum edge matching for reconfigurable computingMarkus Rullmann, Renate Merker. ipps 2006: [doi]

Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration OverheadMarkus Rullmann, Renate Merker. arcs 2006: 132-141

Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word ParallelismRainer Schaffer, Renate Merker. samos 2006: 99-106 [doi]

Derivation of Packing Instructions for Exploiting Sub-Word ParallelismRainer Schaffer, Renate Merker, Francky Catthoor. parelec 2006: 167-172 [doi]

Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two LevelsSebastian Siegel, Rainer Schaffer, Renate Merker. parelec 2006: 173-180 [doi]

Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource ConstraintsSebastian Siegel, Renate Merker. europar 2006: 1181-1191 [doi]

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding RedundancySebastian Siegel, Renate Merker. asap 2006: 28-32 [doi]

2005

2004

2003

A Hardware-Software System for Tomographic ReconstructionJan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer. jcsc, 12(2):203, 2003. [doi]

Causality Constraints for Processor Architectures with Sub-Word ParallelismRainer Schaffer, Renate Merker, Francky Catthoor. dsdm 2003: 82-89 [doi]

2002

Systematic Design of Programs with Sub-Word ParallelismRainer Schaffer, Renate Merker, Francky Catthoor. parelec 2002: 393-398 [doi]

2001

Design of Processor Arrays for Reconfigurable ArchitecturesDirk Fimmel, Renate Merker. tjs, 19(1):41-56, 2001.

2000

1999

1998

Design of Processor Arrays for Real-Time ApplicationsDirk Fimmel, Renate Merker. europar 1998: 1018-1028 [doi]

Determination of processor allocation in the design of processor arraysDirk Fimmel, Renate Merker. mam, 22(3-4):149-155, 1998. [doi]

1997

1996

Propagation of I/O-Variables in Massively Parallel Processor ArraysDirk Fimmel, Renate Merker. pdp 1996: 501-509 [doi]

1994

Systematic Generation of a Variety of Processor ArraysA. Schubert, Renate Merker, H. Schreiber. parcella 1994: 267-276

1990

Systematischer Entwurf und Modellbildung systolischer ArraysRenate Merker. PhD thesis, Dresden University of Technology, Germany, 1990. [doi]

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Publications by 'Renate Merker'

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2011

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