Table of Contents

• Music Technology and Audio Processing: Rall. or Accel. into the Millennium?J. Sundberg. 1
• Two Heads Are Better Than One: Using Diversity to Make Software DependableBev Littlewood. 15
• Industrial Experience ReportG. Turnbull. 21
• The Law of Requisite Holism Systemic versus Reductionistic versus Complex ThinkingMatjaz Mulej. 27
• The Role of the Improvement Manager. Critical Factors Affecting the Development of an Improvement Strategy: Leadership, Organization, Key-Process or Business Results?G. Magnani. 29
• The Future of NetworkingMaurizio Decina. 48
• Digital System Design: Architectures, Methods and ToolsLech Józwiak. 1004 [doi]
• The Changing Semiconductor Industry: From Components to Silicon SystemsTheo A. C. M. Claasen. 1008 [doi]
• Exploiting Data Transfer Locality in Memory MappingPeeter Ellervee, Ahmed Hemani, Miguel Miranda, Francky Catthoor. 1014-1021 [doi]
• Synthesis of Distributed Embedded SystemsKrzysztof Kuchcinski. 1022-1028 [doi]
• Design Space Exploration in System Level Synthesis under Memory ConstraintsRadoslaw Szymanek, Krzysztof Kuchcinski. 1029 [doi]
• Specialized Processor for Channel Allocation in a Cellular Mobile NetworkKi Leung, Adam Postula. 1038-1041 [doi]
• Reconfiguration Mechanism for an IP Block Based InterconnectionKimmo Kuusilinna, Pasi Liimatainen, Timo Hämäläinen, Jukka Saarinen. 1042-1045 [doi]
• Parallelization of Algorithms for a System of Digital Signal ProcessorsMathias Kortke, Dirk Fimmel, Renate Merker. 1046-1050 [doi]
• A Neuro-Fuzzy Real-Time Image Processing SystemClaudio Sansoè, Francesco Gregoretti, Leonardo Maria Reyneri. 1051-1056 [doi]
• Delft-Java Dynamic TranslationC. John Glossner, Stamatis Vassiliadis. 1057-1062 [doi]
• Arithmetic Unit for the Computation of Interval Elementary FunctionsJavier Hormigo, Julio Villalba, Emilio L. Zapata. 1063-1066 [doi]
• Issues of the State Information for Location and Information Policies in Distributed Load Balancing AlgorithmGil-Haeng Lee. 1067-1070 [doi]
• A Pipelined Reconfigurable Architecture for Visual-Based NavigationJose Antonio Boluda, Fernando Pardo, Francisco Blasco, Joan Pelechano. 1071-1074 [doi]
• Hazard Checking in Pipelined Processor Designs Using Symbolic Model CheckingJens Schönherr, Ingo Schreiber, Eva Fordran, Bernd Straube. 1075 [doi]
• Generation of Optimal Universal Logic ModulesRolf Drechsler, Wolfgang Günther. 1080-1085 [doi]
• The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional DecompositionMariusz Rawski, Lech Józwiak, Tadeusz Luba. 1086-1093 [doi]
• Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship MeasuresMariusz Rawski, Lech Józwiak, Tadeusz Luba. 1094-1101 [doi]
• Refined CPLD Macrocell Architecture for the Effective FSM ImplementationValeri Solovjev. 1102 [doi]
• A Novel Approach for CMOS Parallel Counter DesignRong Lin, Kevin E. Kerr, André S. Botha. 1112-1119 [doi]
• A Systolic Library for Solving Matrix EquationsGloria Martínez, Germán Fabregat, Vicente Hernández. 1120-1125 [doi]
• The X-MatchLITE FPGA-Based Data CompressorJose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman. 1126-1132 [doi]
• Implementing a Quantitative Model for the Effective Signal Processing in the Auditory System on a Dedicated Digital VLSI HardwareAlexander Schwarz, Bärbel Mertsching, M. Brucke, Wolfgang Nebel, Jürgen Tchorz, Birger Kollmeier. 1133-1139 [doi]
• A Floating Point Vectoring Algorithm Based on Fast RotationsKees-Jan van der Kolk, Ed F. Deprettere, Jeong-A. Lee. 1140 [doi]
• Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric FunctionsLech Józwiak, Artur Chojnacki. 1150-1160 [doi]
• Logic Restructuring for MUX-Based FPGAsJosé Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías. 1161 [doi]
• Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory ContentionSong Chen, Adam Postula, Lech Józwiak. 1170-1177 [doi]
• A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling MechanismToshinori Sato. 1178-1185 [doi]
• Investigating the Implementation of a Block Structured Architecture in an Early Design StageLieven Eeckhout, Henk Neefs, Koenraad De Bosschere, Jan Van Campenhout. 1186 [doi]
• V-SAT: A Visual Specification and Analysis Tool for System-On-Chip ExplorationAsheesh Khare, Nicolae Savoiu, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau. 1196-1203 [doi]
• A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission LinesGregorio Cappuccino, Giuseppe Cocorullo. 1204-1208 [doi]
• A Reusable Inner Product Unit for DSP ApplicationsM. A. Sacristán, María Victoria Rodellar Biarge, A. Diaz, V. Garcia, Pedro Gómez Vilda. 1209-1213 [doi]
• Esterel and Java in an Object-Oriented Modelling and Simulation Framework for Heterogeneous Software and Hardware Systems The SEP ApproachFrédéric Mallet, Fernand Boéri. 1214 [doi]
• A Selective Compressed Memory System by On-Line Data DecompressingJang-Soo Lee, Won-Kee Hong, Shin-Dug Kim. 1224-1227 [doi]
• Lookahead Cache with Instruction Processing Unit for Filling Memory GapLi San-li, Huang-Zhen Chun. 1228-1231 [doi]
• A Study of Dynamic Instruction Frequencies in Byte Compiled Java ProgramsØyvind Strøm, Audun Klauseie, Einar J. Aas. 1232-1235 [doi]
• Design of Efficient SPARC Cores for Embedded SystemsTomás Bautista, Antonio Núñez. 1236-1239 [doi]
• A Segmented Gray Code for Low-Power Microcontroller Address BusesRolf Hakenes, Yiannos Manoli. 1240-1243 [doi]
• Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power ApplicationsAlessandro De Gloria, Paolo Palma, Mauro Olivieri. 1244-1247 [doi]
• Context-Switching Techniques for Decoupled Multithreaded ProcessorsJochen Kreuzinger, Theo Ungerer. 1248 [doi]
• Self-Testing of S-Compatible Test Units in User-Programmed FPGAsPawel Tomaszewicz, Andrzej Krasniewski. 1254-1259 [doi]
• Application-Dependent Testing of FPGA Delay FaultsAndrzej Krasniewski. 1260-1267 [doi]
• Language Based Design Verification with Semantic AnalysisGeorge Economakos, George K. Papakonstantinou. 1268 [doi]
• Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using DecompositionDariusz Kania. 1278-1281 [doi]
• Results in Comparing Innovative Placement HeuristicsReinhard Rauscher, Dieter Klawan. 1282-1285 [doi]
• The Universal Algorithm for Fitting Targeted to Complex Programmable Logic DevicesValeri Solovjev, Mariusz Chyzy. 1286-1289 [doi]
• High Level Pre-Synthesis Optimization Steps Using Hierarchical Conditional Dependency GraphsApostolos A. Kountouris, Christophe Wolinski. 1290 [doi]
• Low-Energy Directed Architecture Selection and Task Scheduling for System-Level DesignFlavius Gruian, Krzysztof Kuchcinski. 1296-1302 [doi]
• An Improved Scheduling Technique for Time-Triggered Embedded SystemsPaul Pop, Petru Eles, Zebo Peng. 1303-1310 [doi]
• Region Compression: A New Scheme for Memory Energy Minimization in Embedded SystemsLuca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 1311-1317 [doi]
• A Prototyping Method of Embedded Real Time Systems for Signal Processing ApplicationsLuc Bianco, Michel Auguin, Alain Pegatoquet. 1318 [doi]
• Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set MachineTorrey Lewis, Marek A. Perkowski, Lech Józwiak. 1326-1334 [doi]
• Design of a Flexible Coprocessor UnitTill Harbaum, Detlef Meier, Matthias Prinke, Martina Zitterbart. 1335-1342 [doi]
• A Tool for Teaching and Research on Computer Architecture and Reconfigurable SystemsChristof Teuscher, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Eduardo Sanchez, Francisco J. Gómez. 1343 [doi]
• Generic Implementation of DD Packages in MVLRolf Drechsler, Dragan Jankovic, Radomir S. Stankovic. 1352-1359 [doi]
• Checking Integrity During Dynamic Reordering in Decision DiagramsRolf Drechsler. 1360-1367 [doi]
• Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into GatesRafal Rzechowski, Tadeusz Luba, Lech Józwiak. 1368-1375 [doi]
• Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching ActivityIreneusz Brzozowski, Andrzej Kos. 1376 [doi]
• An Interactive Modeling and Generation Tool for the Design of Hw/Sw SystemsF. Muller, Jean Paul Calvez, Dominique Heller, Olivier Pasquier. 1382-1385 [doi]
• Heterogeneous Systems Design: A UML-Based ApproachS. Barrios, J. López. 1386-1387 [doi]
• Unified Modeling Graph for Specifying and Synthesizing Chip-Level InterfacesYoung Moo Lee, Kyu Ho Park. 1388-1389 [doi]
• A Message-Passing Communication Scheme for System SpecificationFrancesco Curatelli, Leonardo Mangeruca, Marco Chirico. 1390-1393 [doi]
• Executable Specification for Multimedia Supporting Refinement and Architecture ExplorationClaus Schneider. 1394-1397 [doi]
• Knowledge Based Specification and Modeling of Embedded SystemsMathias Sporer, Karlheinz Agsteiner, Dieter Monjau, Michael Schwaar. 1398-1401 [doi]
• Modeling Bit Multiplication Blocks for DSP Applications Using VHDLSiddika Berna Örs, Ahmet Dervisoglu. 1402-1405 [doi]
• Application of FHM-Based Design Method to Scalable 2-D DCT ProcessorEiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura. 1406-1409 [doi]
• An Optimization of Simulation Time in the Hardware Accelerated VLSI SimulatorGrzegorz Kucharski, Wlodzimierz Wrona. 1410 [doi]
• A New Destage Algorithm for Disk Cache: DOMEMarina Alonso, Vicente Santonja. 1416-1423 [doi]
• The Filter Cache: A Run-Time Cache Management Approach1Julio Sahuquillo, Ana Pont. 1424-1431 [doi]
• An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization MechanismRyotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata. 1432-1440 [doi]
• Extending Correlation in Branch Prediction SchemesLucian N. Vintan, Colin Egan. 1441-1448 [doi]
• Enhancing Security in the Memory Management UnitTanguy Gilmont, Jean-Didier Legat, Jean-Jacques Quisquater. 1449 [doi]
• A Framework for Retargetable Code Generation Using Simulated AnnealingB. S. Visser. 1458-1462 [doi]
• Software Synthesis for System Level Design Using Process Execution TreesLeo J. van Bokhoven, Jeroen Voeten, Marc Geilen. 1463-1467 [doi]
• HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance EstimationGregor Polansek, Andrej Zemva, Andrej Trost. 1468-1471 [doi]
• Evaluation of Design Space Exploration StrategiesFrancisco Moya, Juan Carlos López, José Manuel Moya. 1472-1476 [doi]
• A Method for Accelerating Test EnvironmentsMatthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn. 1477-1480 [doi]
• Tracing Fault Effects in System EnvironmentJanusz Sosnowski, Piotr Gawkowski. 1481-1486 [doi]
• Linking Codesign and Verification by Means of E-LOTOS FDTPierre Wodey, Fabrice Baray. 1487-1491 [doi]
• A Hardware/Software Cosimulation Environment for DSP ApplicationsChristian Kreiner, Christian Steger, Reinhold Weiss. 1492-1495 [doi]
• System Level Models for Real-Time CommunicationP. H. A. van der Putten, Jeroen Voeten, Marc Geilen, M. P. J. Stevens. 1496 [doi]
• A Unified Algorithm for Mutual Exclusiveness IdentificationOlga Peñalba, José M. Mendías, Román Hermida. 1504-1510 [doi]
• Application of Multidimensional Retiming and Matroid Theory to DSP Algorithm ParallelizationFelipe Fernández, Ángel Sánchez. 1511-1518 [doi]
• VHDL Description and High-Level Synthesis of an ATM Layer CircuitWalter Lange, Wolfgang Rosenstiel. 1519 [doi]
• Workshop Chair Introduction: Music Technology and Audio ProcessingDavid M. Howard. 2004 [doi]
• Radical User Interfaces for Real-Time ControlAndy Hunt, Ross Kirk. 2006-2012 [doi]
• Motion Curves in Music: The Statistical Analysis of Midi DataM. Das, David M. Howard, Stephen L. Smith. 2013-2019 [doi]
• Using Music Performance Software with Flexible Control Interfaces for Live Performance by Severely Disabled MusiciansTim Anderson. 2020 [doi]
• A New Music Technology System to Teach MusicA. Lassauniere, J. Marchant, A. Close, G. E. Tewkesbury, D. A. Sanders. 2030-2034 [doi]
• Project Patron: Exploiting a Digital Library for the Performing ArtsJon Maslin, Elizabeth Lyon. 2035-2041 [doi]
• Distance Learning Support for Teaching Musical TemperamentPaul E. Garner, David M. Howard. 2042 [doi]
• A Novel Efficient Algorithm for Music TranspositionBob Lawlor, A. D. Fagan. 2048-2054 [doi]
• Perfect Audio Signal Processing using Finite Field TransformsJames A. S. Angus. 2055-2060 [doi]
• A Framework for Audio Analysis based on Classification and Temporal SegmentationGeorge Tzanetakis, Perry R. Cook. 2061 [doi]
• A Parallel Processing System for Polyphonic Singing SynthesisIan Gibson, David M. Howard, Andrew M. Tyrrell. 2070-2074 [doi]
• The Chorus Effect Revisited: Experiments in Frequency-Domain Analysis and Simulation of Ensemble SoundsDaniel Kahlin, Sten Ternström. 2075 [doi]
• Digital Waveguide Modelling of Room Acoustics: Comparing Mesh TopologiesDavid M. Howard. 2082 [doi]
• Workshop Chair Introduction: Dependable Computing SystemsJulian M. Bass. 2094 [doi]
• A Software Library, A Control Backbone and User-Specified Recovery Strategies to Enhance the Dependability of Embedded SystemsGeert Deconinck, Vincenzo De Florio, Rudy Lauwereins, Ronnie Belmans. 2098-2104 [doi]
• Error Recovery using Forced Validity Assisted by Executable Assertions for Error Detection: An Experimental EvaluationMartin Hiller. 2105-2112 [doi]
• Adaptive Majority Voter: A Novel Voting Algorithm for Real-Time Fault-Tolerant Control SystemsG. Latif-Shabgahi, Stuart Bennett. 2113 [doi]
• The Komodo Project: Thread-based Event Handling Supported by a Multithreaded Java MicrocontrollerJochen Kreuzinger, R. Marston, Theo Ungerer, Uwe Brinkschulte, C. Krakowski. 2122-2128 [doi]
• Computer Know Thy Self!: A Biological Way to Look at Fault-ToleranceAndrew M. Tyrrell. 2129 [doi]
• Decomposition Technique for Integrated Dependability Evaluation of Hardware-Software Systems Using Stochastic Activity NetworksYudi Purwantoro, Stuart Bennett. 2142-2145 [doi]
• An Experimental Comparison of Software Diagnosis MethodsMaisaa Khalil, Oum-El-Kheir Benkahla, Chantal Robach. 2146-2149 [doi]
• A Design Tool for Dependable Video on Demand ApplicationsLuigi Romano, Antonio Coronato, Antonino Mazzeo, Nicola Mazzocca. 2150 [doi]
• Workshop Chair Introduction: Software Process and Product ImprovementGerhard Ghroust. 2158 [doi]
• What the Softward Industry Says about the Practices Modelled in Current Softward Process Models?Yingxu Wang, Graham King, Hakan Wickberg, Alec Dorling. 2162 [doi]
• The Role of Culture in Successful Software Process ImprovementHelen Sharp, Mark Woodman, Fiona Hovenden, Hugh Robinson. 2170 [doi]
• An Experiment to Improve Cost Estimation and Project Tracking for Software and Systems Integration ProjectsBrian W. Chatters, Peter Henderson, Chris Rostron. 2177-2184 [doi]
• Experiences from the Pilot Operation and Commissioning Phase of a SCM Process Improvement ProgramMinna Nättinen, Tua Rahikkala, Antti Välimäki. 2185 [doi]
• PSEEs Modelling for Supporting and Improving Collaborative Joint Software Development ProjectsPierre Fernand Tiako, Jean-Claude Derniame. 2194-2201 [doi]
• A Tool for Testing Hypermedia SystemsHareton K. N. Leung. 2202-2209 [doi]
• A Distributed Tool for Commitment Specification and ManagementAyça Tarhan, Elif Demirörs, Onur Demirörs. 2210 [doi]
• Design Patterns for Component-Oriented Software DevelopmentKarl Rege. 2220-2228 [doi]
• Extendable Object Visualisation for Software ReengineeringJörg R. Mühlbacher, Peter R. Dietmüller, Markus Jöbstl. 2229-2236 [doi]
• Validation of Object Oriented Models using AnimationIan Oliver, Stuart Kent. 2237 [doi]
• Requirements Change: A Dissection of Management IssuesW. Lam, V. Shankararaman. 2244-2251 [doi]
• Capturing, Negotiating, and Evolving System Requirements: Bridging WinWin and the UMLJosé Parets-Llorca, Paul Grünbacher. 2252-2259 [doi]
• Processing Requirements by Software Configuration ManagementIvica Crnkovic, Peter J. Funk, Magnus Larsson. 2260 [doi]
• Experience in Comparative Process Assessment with Multi-Process-ModelsYingxu Wang, Alec Dorling, Hakan Wickberg, Graham King. 2268-2273 [doi]
• A Lean Metric Acquisition and Presentation Environment for the Assessment of a Test Process Improvement ExperimentPhilipp Jocham, Christian Kreiner. 2274-2278 [doi]
• Automating SCM Metric Data Collection and Analysis in Virtual Software CorporationsJussi Ronkainen, Tua Rahikkala, Rod Blackwood. 2279 [doi]
• Multi-Agent Environment for Software Quality Assurance, AUTOQHareton K. N. Leung, Connie Poon. 2294 [doi]
• Workshop Chair Introduction: Multimedia and TelecommunicationsFrédéric Patricelli. 2306 [doi]
• Semi-Structured Data Extraction and Schema Knowledge MiningEnhong Chen, Xufa Wang. 2310-2317 [doi]
• Hardwired Paeth Codec for Portable Network Graphics (PNG)Edwin A. Hakkennes, Stamatis Vassiliadis. 2318-2325 [doi]
• A Dictionary-Adaptive Speech Driven User Interface for a Distributed Multimedia PlatformJohannes Peltola, Johan Plomp, Tapio Seppänen. 2326 [doi]
• Design of Distributed System Protocols based on Standard FDL sPerfecto Mariño, Miguel Angel Domínguez, Francisco Poza, Juan B. Nogueira. 2334-2341 [doi]
• Carrying ATM Cells over EthernetJ. M. Arco, A. Martínez, B. Alarcos, A. García, Daniel Meziat. 2342-2349 [doi]
• Dealing with Non-Determinism in Communications within Java ApplicationsAlessio Bechini, Raffaele Lapadula, Cosimo Antonio Prete. 2350 [doi]
• Delay Performance Measurements in Multimedia SwitchingTimo Hämäläinen. 2360-2366 [doi]
• Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks SimulationJuanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta. 2367-2374 [doi]
• Improved Hard Acknowledgement Deadline Protocol in Real-Time RPCHan Namgoong, Myung-Joon Kim. 2375 [doi]
• Combining Motion Estimation with Feature Extraction in MPEG Video CodersPierpaolo Baglietto, A. L. Frisiani. 2384-2391 [doi]
• Neural Network based Textural Labeling of Images in Multimedia ApplicationsS. A. Karkanis, George D. Magoulas, Maria Grigoriadou, Dimitris A. Karras. 2392 [doi]
• Communicating Spatial Information via a Multimedia-Auditory InterfaceDimitrios I. Rigas, D. Hopwood, Dave Memery. 2398-2405 [doi]
• Balancing the Multimedia Mix in a Large Scale Distance Education CourseMark Woodman, Josie Taylor. 2406-2414 [doi]
• Results of an Elliptic-Curve-Approach for Use in CryptosystemsReinhard Rauscher, Frank Bohnsack. 2415 [doi]
• Workshop Chair Introduction : Special Session on Network ComputingDjamshid Tavangarian, Ferenc Vajda. 2426 [doi]
• Parallel Computing using Java Mobile AgentsChristoforos Panayiotou, George Samaras, Evaggelia Pitoura, Paraskevas Evripidou. 2430-2437 [doi]
• PVM Parameter Tuning to Improve Communication in Distributed ApplicationsMaurizio Giordano, Mario Mango Furnari, Francesco Vitobello. 2438-2445 [doi]
• A Distributed Algorithm for k-way Graph PartitioningSandeep Koranne. 2446 [doi]
• JFS: A Secure Distributed File System for Network ComputersMarcus O Connell, Paddy Nixon. 2450-2457 [doi]
• Implementing Multiparty Interactions on a Network ComputerRafael Corchuelo, David Ruiz, Miguel Toro, Antonio Ruiz Cortés. 2458-2465 [doi]
• Locust - A Brokerage System for Accessing Idle Ressources for Web-ComputingMichael May. 2466-2475 [doi]