Toshio Shimada - researchr alias

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Viewing Publication 1 - 25 from 25

2008

Power consumption reduction scheme focusing on the Depth of Speculative ExecutionHideki Oshima, Ryotaro Kobayashi, Kazuki Shimura, Toshio Shimada. IEEEcit 2008: 207-212 [doi]

Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-CalculationAkihiro Yamamoto, Yusuke Tanaka 0001, Hideki Ando, Toshio Shimada. imt, 3(4):755-767, 2008. [doi]

2007

Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocationAkihiro Yamamoto, Yusuke Tanaka 0001, Hideki Ando, Toshio Shimada. medea 2007: 33-40 [doi]

2006

Limits of Thread-Level Parallelism in Non-numerical ProgramsAkio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada. imt, 1:851-859, 2006. [doi]

Limits of Thread-Level Parallelism in Non-numerical ProgramsAkio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada. imt, 1(2):851-859, 2006. [doi]

2003

Pipeline stage unification: a low-energy consumption technique for future mobile processorsHajime Shimada, Hideki Ando, Toshio Shimada. islped 2003: 326-329 [doi]

2002

A preactivating mechanism for a VT-CMOS cache using address predictionRyo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada. islped 2002: 247-250 [doi]

1999

1993

Empirical Study of Latency Hiding on a Fine-Grain Parallel ProcessorKei Hiraki, Toshio Shimada, Satoshi Sekiguchi. ics 1993: 220-229 [doi]

The Hardware Architecture of the CODA Real-Time Parallel ProcessorKenji Nishida, Kenji Toda, Toshio Shimada, Yoshinori Yamaguchi. parco 1994: 395-402

1992

Real-Time Parallel Architecture for Sensor FunsionToshio Shimada, Kenji Toda, Kenji Nishida. jpdc, 15(2):143-152, 1992.

A priority forwarding scheme for real-time multistage interconnection networksKenji Toda, Kenji Nishida, Shuichi Sakai, Toshio Shimada. rtss 1992: 208-217 [doi]

1991

Sequential description and parallel execution language DFCII dataflow supercomputersSatoshi Sekiguchi, Toshio Shimada, Kei Hiraki. ics 1991: 57-66 [doi]

Parallel Multi-Context Architecture with High-Speed Synchronization MechanismKenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada. ipps 1991: 336-343

1990

Dataflow computer development in JapanToshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai. ics 1990: 140-147 [doi]

1989

Data flow language DFC: Design and implementationToshio Shimada, Satoshi Sekiguchi, Kei Hiraki. scjapan, 20(6):1-10, 1989. [doi]

1988

Efficient vector processing on dataflow supercomputer SIGMA-1Kei Hiraki, Satoshi Sekiguchi, Toshio Shimada. sc 1988: 374-381 [doi]

1987

Load scheduling schemes using inter - PE networkKei Hiraki, Satoshi Sekiguchi, Toshio Shimada. scjapan, 18(1):55-66, 1987. [doi]

The SIGMA-1 dataflow computerToshitsugu Yuba, Kei Hiraki, Toshio Shimada, Satoshi Sekiguchi, Kenji Nishida. fjcc 1987: 578-585 [doi]

1986

Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of ProcessorsKei Hiraki, Kenji Nishida, Satoshi Sekiguchi, Toshio Shimada. icpp 1986: 584-591

Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific ComputationsToshio Shimada, Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi. isca 1986: 226-234

1984

Evaluation of Associative Memory Using Parallel Chained HashingKei Hiraki, Kenji Nishida, Toshio Shimada. TC, 33(9):851-855, 1984.

An Architecture of a Data Flow Machine and Its EvaluationToshio Shimada, Kei Hiraki, Kenji Nishida. compcon 1984: 486-490

1983

A Control Mechanism of a Lisp-Based Data-Driven MachineToshitsugu Yuba, Yoshinori Yamaguchi, Toshio Shimada. ipl, 16(3):139-143, 1983.

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