Hideki Ando - researchr alias

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Viewing Publication 1 - 36 from 36

2024

Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue QueueKenichiro Mori, Sota Kosugi, Hiroto Yoshida, Hajime Shimada, Hideki Ando. micro 2024: 493-506 [doi]

2022

Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and AreaHideki Ando. iccd 2022: 360-363 [doi]

Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag ComparisonYasutaka Matsuda, Ryota Shioya, Hideki Ando. ieicetd, 105(2):320-332, 2022. [doi]

2019

SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular QueueHideki Ando. micro 2019: 506-518 [doi]

Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch PipelineReoma Matsuo, Ryota Shioya, Hideki Ando. cal, 18(2):170-173, 2019. [doi]

2018

2016

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS ControlHideki Ando, Ryota Shioya. ieicet, 99-D(2):341-350, 2016. [doi]

FXA: Executing Instructions in Front-End for Energy EfficiencyRyota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando. ieicet, 99-D(4):1092-1107, 2016. [doi]

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy EfficiencyRyota Shioya, Hideki Ando. ieicet, 99-D(3):630-640, 2016. [doi]

2014

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available ParallelismYuya Kora, Kyohei Yamaguchi, Hideki Ando. ieicet, 97-D(12):3110-3123, 2014. [doi]

Energy efficiency improvement of renamed trace cache through the reduction of dependent path lengthRyota Shioya, Hideki Ando. iccd 2014: 416-423 [doi]

A Front-End Execution Architecture for High Energy EfficiencyRyota Shioya, Masahiro Goshima, Hideki Ando. micro 2014: 419-431 [doi]

2013

MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLPYuya Kora, Kyohei Yamaguchi, Hideki Ando. micro 2013: 37-48 [doi]

2012

Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path IdentificationKyohei Yamaguchi, Yuya Kora, Hideki Ando. ieicet, 95-D(9):2235-2246, 2012. [doi]

2011

Evaluation of issue queue delay: Banking tag RAM and identifying correct critical pathKyohei Yamaguchi, Yuya Kora, Hideki Ando. iccd 2011: 313-319 [doi]

2010

Register File Size Reduction through Instruction Pre-Execution Incorporating Value PredictionYusuke Tanaka, Hideki Ando. ieicet, 93-D(12):3294-3305, 2010. [doi]

2009

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register DeallocationKazunaga Hyodo, Kengo Iwamoto, Hideki Ando. ieicet, 92-D(11):2186-2195, 2009. [doi]

Reducing register file size through instruction pre-execution enhanced by value predictionYusuke Tanaka, Hideki Ando. iccd 2009: 238-245 [doi]

2008

Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-CalculationAkihiro Yamamoto, Yusuke Tanaka 0001, Hideki Ando, Toshio Shimada. imt, 3(4):755-767, 2008. [doi]

2007

Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocationAkihiro Yamamoto, Yusuke Tanaka 0001, Hideki Ando, Toshio Shimada. medea 2007: 33-40 [doi]

2006

Limits of Thread-Level Parallelism in Non-numerical ProgramsAkio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada. imt, 1:851-859, 2006. [doi]

Limits of Thread-Level Parallelism in Non-numerical ProgramsAkio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada. imt, 1(2):851-859, 2006. [doi]

2003

Pipeline stage unification: a low-energy consumption technique for future mobile processorsHajime Shimada, Hideki Ando, Toshio Shimada. islped 2003: 326-329 [doi]

2002

A preactivating mechanism for a VT-CMOS cache using address predictionRyo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada. islped 2002: 247-250 [doi]

1999

Distributed memoryless point convergence algorithm for mobile robots with limited visibilityHideki Ando, Yoshinobu Oasa, Ichiro Suzuki, Masafumi Yamashita. trob, 15(5):818-828, 1999. [doi]

An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization MechanismRyotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata. euromicro 1999: 1432-1440 [doi]

1998

Software pipelining with path selectionChikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya. scjapan, 29(9):74-86, 1998. [doi]

1996

Performance Comparison of ILP Machines with Cycle Time EvaluationTetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya. isca 1996: 213-224 [doi]

1995

Unconstrained Speculative Execution with Predicated State BufferingHideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya. isca 1995: 126-137 [doi]

Code scheduling on a superscalar processor: SARCHChikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya. scjapan, 26(9):13-22, 1995. [doi]

1993

1988

A DSP line equalizer VLSI for TCM digital subscriber-line transmissionHideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba. jssc, 23(1):118-123, February 1988. [doi]

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