Table of Contents

• Quality programmable vector processors for approximate computingSwagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan. 1-12 [doi]
• SAGE: self-tuning approximation for graphics enginesMehrzad Samadi, Janghaeng Lee, D. Anoushe Jamshidi, Amir Hormati, Scott A. Mahlke. 13-24 [doi]
• Approximate storage in solid-state memoriesAdrian Sampson, Jacob Nelson, Karin Strauss, Luis Ceze. 25-36 [doi]
• MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLPYuya Kora, Kyohei Yamaguchi, Hideki Ando. 37-48 [doi]
• TLC: a tag-less cache for reducing dynamic first level cache energyAndreas Sembrant, Erik Hagersten, David Black-Schaffer. 49-61 [doi]
• Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed cachingSomayeh Sardashti, David A. Wood. 62-73 [doi]
• Exploiting GPU peak-power and performance tradeoffs through reduced effective pipeline latencySyed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte. 74-85 [doi]
• A locality-aware memory hierarchy for energy-efficient GPU architecturesMinsoo Rhu, Michael Sullivan, Jingwen Leng, Mattan Erez. 86-98 [doi]
• Divergence-aware warp schedulingTimothy G. Rogers, Mike O'Connor, Tor M. Aamodt. 99-110 [doi]
• Warped gates: gating aware scheduling and power gating for GPGPUsMohammad Abdel-Majeed, Daniel Wong 0001, Murali Annavaram. 111-122 [doi]
• Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detectionRaghuraman Balasubramanian, Karthikeyan Sankaralingam. 123-135 [doi]
• Use it or lose it: wear-out and lifetime in future chip multiprocessorsHyungJun Kim, Arseniy Vitkovskiy, Paul V. Gratz, Vassos Soteriou. 136-147 [doi]
• uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faultsRitesh Parikh, Valeria Bertacco. 148-159 [doi]
• Implicit-storing and redundant-encoding-of-attribute information in error-correction-codesYiannakis Sazeides, Emre Özer, Danny Kershaw, Panagiota Nikolaou, Marios Kleanthous, Jaume Abella. 160-171 [doi]
• Linearly compressed pages: a low-complexity, low-latency main memory compression frameworkGennady Pekhimenko, Vivek Seshadri, Yoongu Kim, Hongyi Xin, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry. 172-184 [doi]
• RowClone: fast and energy-efficient in-DRAM bulk data copy and initializationVivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry. 185-197 [doi]
• Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory deviceManjunath Shevgoor, Jung Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha N. Udipi. 198-209 [doi]
• Crank it up or dial it down: coordinated multiprocessor frequency and folding controlAugusto Vega, Alper Buyuktosunoglu, Heather Hanson, Pradip Bose, Srinivasan Ramani. 210-221 [doi]
• Wavelength stealing: an opportunistic approach to channel sharing in multi-chip photonic interconnectsArslan Zulfiqar, Pranay Koka, Herb Schwetman, Mikko H. Lipasti, Xuezhe Zheng, Ashok V. Krishnamoorthy. 222-233 [doi]
• DESC: energy-efficient data exchange using synchronized countersMahdi Nazm Bojnordi, Engin Ipek. 234-246 [doi]
• Linearizing irregular memory accesses for improved correlated prefetchingAkanksha Jain, Calvin Lin. 247-259 [doi]
• RDIP: return-address-stack directed instruction prefetchingAasheesh Kolli, Ali G. Saidi, Thomas F. Wenisch. 260-271 [doi]
• SHIFT: shared history instruction fetch for lean-core server processorsCansu Kaynak, Boris Grot, Babak Falsafi. 272-283 [doi]
• Insertion and promotion for tree-based PseudoLRU last-level cachesDaniel A. Jiménez. 284-296 [doi]
• Imbalanced cache partitioning for balanced data-parallel programsAbhisek Pan, Vijay S. Pai. 297-309 [doi]
• The reuse cache: downsizing the shared last-level cacheJorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería. 310-321 [doi]
• Enabling datacenter servers to scale out economically and sustainablyChao Li, Yang Hu, Ruijin Zhou, Ming Liu, Longjun Liu, Jingling Yuan, Tao Li. 322-333 [doi]
• Efficient multiprogramming for multicores with SCAFTimothy Creech, Aparna Kotha, Rajeev Barua. 334-345 [doi]
• Allocating rotating registers by schedulingHongbo Rong, Hyunchul Park, Cheng Wang, Youfeng Wu. 346-358 [doi]
• Multi-grain coherence directoriesJason Zebchuk, Babak Falsafi, Andreas Moshovos. 359-370 [doi]
• BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environmentXuehai Qian, Josep Torrellas, Benjamin Sahelices, Depei Qian. 371-382 [doi]
• Large-reach memory management unit cachesAbhishek Bhattacharjee. 383-394 [doi]
• Efficient management of last-level caches in graphics processors for 3D scene rendering workloadsJayesh Gaur, Raghuram Srinivasan, Sreenivas Subramoney, Mainak Chaudhuri. 395-407 [doi]
• Energy efficient GPU transactional memory via space-time optimizationsWilson W. L. Fung, Tor M. Aamodt. 408-420 [doi]
• Kiln: closing the performance gap between systems with and without persistence supportJishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, Norman P. Jouppi. 421-432 [doi]
• Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memoryJie Fan, Song Jiang, Jiwu Shu, Youhui Zhang, Weimin Zhen. 433-444 [doi]
• Trace based phase prediction for tightly-coupled heterogeneous coresShruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke. 445-456 [doi]
• Heterogeneous system coherence for integrated CPU-GPU systemsJason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, David A. Wood. 457-467 [doi]
• Meet the walkers: accelerating index traversals for in-memory databasesYusuf Onur Koçberber, Boris Grot, Javier Picorel, Babak Falsafi, Kevin T. Lim, Parthasarathy Ranganathan. 468-479 [doi]