Table of Contents

• CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed CacheChia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi. 1-12 [doi]
• Transparent Hardware Management of Stacked DRAM as Part of MemoryJaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim. 13-24 [doi]
• Unison Cache: A Scalable and Effective Die-Stacked DRAM CacheDjordje Jevdjic, Gabriel H. Loh, Cansu Kaynak, Babak Falsafi. 25-37 [doi]
• Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and BandwidthNagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan. 38-50 [doi]
• Citadel: Efficiently Protecting Stacked Memory from Large Granularity FailuresPrashant Nair, David A. Roberts, Moinuddin K. Qureshi. 51-62 [doi]
• Locality-Aware Mapping of Nested Parallel Patterns on GPUsHyoukJoong Lee, Kevin J. Brown, Arvind K. Sujeeth, Tiark Rompf, Kunle Olukotun. 63-74 [doi]
• Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware WorklistsJi-Yun Kim, Christopher Batten. 75-87 [doi]
• PORPLE: An Extensible Optimizer for Portable Data Placement on GPUGuoyang Chen, Bo Wu, Dong Li, Xipeng Shen. 88-100 [doi]
• Exploring the Design Space of SPMD Divergence Management on Data-Parallel ArchitecturesYunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, Krste Asanovic. 101-113 [doi]
• Managing GPU Concurrency in Heterogeneous ArchitecturesOnur Kayiran, Nachiappan Chidambaram Nachiappan, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das. 114-126 [doi]
• Load Value ApproximationJoshua San Miguel, Mario Badr, Natalie D. Enright Jerger. 127-139 [doi]
• Arbitrary Modulus IndexingJeffrey R. Diamond, Donald S. Fussell, Stephen W. Keckler. 140-152 [doi]
• FIRM: Fair and High-Performance Memory Control for Persistent Memory SystemsJishen Zhao, Onur Mutlu, Yuan Xie 0001. 153-165 [doi]
• Short-Circuiting Memory Traffic in Handheld PlatformsPraveen Yedlapalli, Nachiappan Chidambaram Nachiappan, Niranjan Soundararajan, Anand Sivasubramaniam, Mahmut T. Kandemir, Chita R. Das. 166-177 [doi]
• Efficient Memory Virtualization: Reducing Dimensionality of Nested Page WalksJayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift. 178-189 [doi]
• Iso-X: A Flexible Architecture for Hardware-Managed Isolated ExecutionDmitry Evtyushkin, Jesse Elwell, Meltem Ozsoy, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh, Ryan Riley. 190-202 [doi]
• Random Fill Cache ArchitectureFangfei Liu, Ruby B. Lee. 203-215 [doi]
• CC-Hunter: Uncovering Covert Timing Channels on Shared Processor HardwareJie Chen 0020, Guru Venkataramani. 216-228 [doi]
• Continuous, Low Overhead, Run-Time Validation of Program ExecutionsErdem Aktas, Furat Afram, Kanad Ghose. 229-241 [doi]
• A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level EventsRobert Callan, Alenka G. Zajic, Milos Prvulovic. 242-254 [doi]
• RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event StacksJaewon Lee, Hanhwi Jang, Jangwoo Kim. 255-267 [doi]
• GPUMech: GPU Performance Modeling Technique Based on Interval AnalysisJen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee. 268-279 [doi]
• PyMTL: A Unified Framework for Vertically Integrated Computer Architecture ResearchDerek Lockhart, Gary Zibrat, Christopher Batten. 280-292 [doi]
• Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient FaultsMark Wilkening, Vilas Sridharan, Si Li, Fritz Previlon, Sudhanva Gurumurthi, David R. Kaeli. 293-305 [doi]
• Using ECC Feedback to Guide Voltage Speculation in Low-Voltage ProcessorsAnys Bacha, Radu Teodorescu. 306-318 [doi]
• Harnessing Soft Computations for Low-Budget Fault ToleranceDaya Shanker Khudia, Scott A. Mahlke. 319-330 [doi]
• Skewed Compressed CachesSomayeh Sardashti, André Seznec, David A. Wood. 331-342 [doi]
• Adaptive Cache Management for Energy-Efficient GPU ComputingXuhao Chen, Li-Wen Chang, Christopher I. Rodrigues, Jie Lv, Zhiying Wang, Wen-mei W. Hwu. 343-355 [doi]
• Futility Scaling: High-Associativity Cache PartitioningRuisheng Wang, Lizhong Chen. 356-367 [doi]
• Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization OpportunitiesRamon Bertran, Alper Buyuktosunoglu, Pradip Bose, Timothy J. Slegel, Gerard Salem, Sean M. Carey, Richard F. Rizzolo, Thomas Strach. 368-380 [doi]
• Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution NetworksWaclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa B. Apsel, Christopher Batten. 381-393 [doi]
• Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated SystemsJeongseob Ahn, Chang-Hyun Park, Jaehyuk Huh. 394-405 [doi]
• SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale ComputersYunqi Zhang, Michael A. Laurenzano, Jason Mars, Lingjia Tang. 406-418 [doi]
• A Front-End Execution Architecture for High Energy EfficiencyRyota Shioya, Masahiro Goshima, Hideki Ando. 419-431 [doi]
• Execution Drafting: Energy Efficiency through Computation DeduplicationMichael McKeown, Jonathan Balkind, David Wentzlaff. 432-444 [doi]
• PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space ExplorationBo Su, Junli Gu, Li Shen, Wei Huang, Joseph L. Greathouse, Zhiying Wang. 445-457 [doi]
• NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?Natalie D. Enright Jerger, Ajaykumar Kannan, Zimo Li, Gabriel H. Loh. 458-470 [doi]
• Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle ArbitrationSupreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David Blaauw. 471-483 [doi]
• Multi-GPU System Design with Memory NetworksGwangsun Kim, Minseok Lee, Jiyun Jeong, John Kim. 484-495 [doi]
• Dodec: Random-Link, Low-Radix On-Chip NetworksHaoFan Yang, Jyoti Tripathi, Natalie D. Enright Jerger, Dan Gibson. 496-508 [doi]
• Wormhole: Wisely Predicting Multidimensional BranchesJorge Albericio, Joshua San Miguel, Natalie D. Enright Jerger, Andreas Moshovos. 509-520 [doi]
• Bias-Free Branch PredictorDibakar Gope, Mikko H. Lipasti. 521-532 [doi]
• Loop-Aware Memory Prefetching Using Code Block Working SetsAdi Fuchs, Shie Mannor, Uri C. Weiser, Yoav Etsion. 533-544 [doi]
• BuMP: Bulk Memory Access Prediction and StreamingStavros Volos, Javier Picorel, Babak Falsafi, Boris Grot. 545-557 [doi]
• Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale ComputersMichael A. Laurenzano, Yunqi Zhang, Lingjia Tang, Jason Mars. 558-570 [doi]
• Compiler Support for Optimizing Memory Bank-Level ParallelismWei Ding, Diana Guttman, Mahmut T. Kandemir. 571-582 [doi]
• Architectural Specialization for Inter-Iteration Loop Dependence PatternsShreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten. 583-595 [doi]
• Specializing Compiler Optimizations through Programmable Composition for Dense Matrix ComputationsQing Yi, Qian Wang, Huimin Cui. 596-608 [doi]
• DaDianNao: A Machine-Learning SupercomputerYunji Chen, Tao Luo, Shaoli Liu, Shijin Zhang, Liqiang He, Jia Wang, Ling Li, Tianshi Chen, Zhiwei Xu, Ninghui Sun, Olivier Temam. 609-622 [doi]
• B-Fetch: Branch Prediction Directed Prefetching for Chip-MultiprocessorsDavid Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel A. Jiménez. 623-634 [doi]
• Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency ModelsDaniel Lustig, Michael Pellauer, Margaret Martonosi. 635-646 [doi]
• Equalizer: Dynamic Tuning of GPU Resources for Efficient ExecutionAnkit Sethia, Scott A. Mahlke. 647-658 [doi]
• COMP: Compiler Optimizations for Manycore ProcessorsLinhai Song, Min Feng, Nishkam Ravi, Yi Yang, Srimat T. Chakradhar. 659-671 [doi]