Abstract is missing.
- Symbolic Analysis Methods for Masks, Circuits, and SystemsRandal E. Bryant. 6-8
- Wearable Computers: Merging Information Space with the WorkspaceDaniel P. Siewiorek. 10-11
- Design for Testability: Today and in the FutureThomas W. Williams. 14
- A Recursive Technique for Computing Lower-Bound Performance of SchedulesMichel Langevin, Eduard Cerny. 16-20
- Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow GraphsYuan Hu, Ahmed Ghouse, Bradley S. Carlson. 21-24
- The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling ProblemSamit Chaudhuri, Robert A. Walker, John Mitchell. 25-29
- A Split Data Cache for Superscalar ProcessorsRodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe. 32-39
- About Set and Skewed Associativity on Second-Level CachesAndré Seznec. 40-43
- An Intelligent I-Cache Prefetch MechanismHonesty C. Young, Eugene J. Shekita. 44-49
- Hardware Verification Using Symbolic State Transition GraphsPinhong Chen, Jyuo-Min Shyu, Liang-Gee Chen. 54-57
- Towards a Methodology for the Formal Hierarchical VerificationSofiène Tahar, Ramayya Kumar. 58-62
- AMBIANT: Automatic Generation of Behavioral Modifications for TestabilityPraveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir. 63-66
- An Analysis of Path Sensitization CriteriaJoão P. Marques Silva, Karem A. Sakallah. 68-72
- A Path Sensitization Approach to Area ReductionHsi-Chuan Chen, Siu-Wing Cheng, Yaun-chung Hsu, David Hung-Chang Du. 73-76
- Statistical Timing Optimization of Combinatorial Logic CircuitsHorng-Fei Jyu, Sharad Malik. 77-80
- Fidelity and Near-Optimality of Elmore-Based Routing ConstructionsKenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins. 81-84
- Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000Trung A. Diep, Mikko H. Lipasti, John Paul Shen. 86-93
- Determining Cost-Effective Multiple Issue Processor DesignsThomas M. Conte, William H. Mangione-Smith. 94-101
- Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt MethodsChia-Jiu Wang, Frank Emnett. 102-105
- Speculative Execution and Reducing Branch Penalty in a Parallel Issue MachineHideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya. 106-113
- Speculative Computation for Coprocessor SynthesisUlrich Holtmann, Rolf Ernst. 126-131
- Evaluation of an Object-Caching Coprocessor Design for Object-Oriented SystemsJ. Morris Chang, Edward F. Gehringer. 132-139
- The Spring Scheduling Co-Processor: A Scheduling AcceleratorWayne Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems. 140-144
- A Partial Scan Cost Estimation Method at the System LevelScott Chiu, Christos A. Papachristou. 146-150
- Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial ScanSandeep Bhatia, Niraj K. Jha. 151-154
- Bit-Splitting for Testability Enhancement in Scan-Based DesignXiaodong Xie, Alexander Albicki. 155-158
- ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic CircuitsChin-Long Wey, Ming-Der Shieh, P. David Fisher. 159-162
- An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent SystemsTod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello. 166-173
- An Efficient Unique State Coding Algorithm for Signal Transition GraphsEnric Pastor, Jordi Cortadella. 174-177
- A Comparison of Synchronous and Asynchronous FSMD DesignsRichard Auletta, Robert B. Reese, Cherrice Traver. 178-182
- SMAC: A Scene Matching ChipN. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer. 184-187
- Fault-Tolerant Content Addressable MemoryJien-Chung Lo. 193-196
- A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS TechnologyDebabrata Ghosh, S. K. Nandy. 198-201
- A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary ArchitectureHiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara. 202-205
- A C-Testable Carry-Free DividerHosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi. 206-213
- A New High Performance Field Programmable Gate Array FamilyTelle Whitney, Jeff Schlageter. 216-219
- Channel Architecture Optimization for Performance and Routability of Row-Based FPGAsKaushik Roy, Sudip Nag, Santanu Dutta. 220-223
- Efficient Verification of Symmetric Concurrent SystemsC. Norris Ip, David L. Dill. 230-234
- Specification and Synthesis of Mixed-Mode Systems: Experiments in a VHDL EnvironmentP. A. Subrahmanyam, Josep M. Espinalt, Meng-Lin Yu. 235-241
- Synthesis of Controllers from Interval Temporal Logic SpecificationMasahiro Fujita, Shinji Kono. 242-245
- The PowerPC 601 Design MethodologyTimothy B. Brodnax, Mike Schiffli, Floyd Watson. 248-252
- Design Methodology for GMICRO:::TM:::/500 TRON MicroprocessorSusumu Narita, Fumio Arakawa, Kunio Uchiyama, Ikuya Kawasaki. 253-257
- Design of the Intel Pentium:::TM::: ProcessorAvtar Saini. 258-261
- VLSI Design of On-Line Add/Multiply AlgorithmsAli Skaf, Alain Guyot. 264-267
- Hybrid Number Representations with Bounded Carry Propagation ChainsDhananjay S. Phatak, Israel Koren, Hoon Choi. 272-275
- A Three-Dimensional Mesh Multiprocessor System Using Board-to-Board Free-Space Optical Interconnects: COSINE-IIIToshikazu Sakano, Takao Matsumoto, Kazuhiro Noguchi. 278-283
- A Vector Memory System Based on Wafer-Scale Integrated Memory ArraysTzi-cker Chiueh. 284-288
- A Novel Clock Distribution System for CMOS VLSIK. Ishibashi, T. Hayashi, T. Doi, N. Masuda, A. Yamagiwa, T. Okabe. 289-292
- An Efficient Symbolic Design Verification SystemJaehong Park, M. Ray Mercer. 294-298
- Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition RelationGianpiero Cabodi, Paolo Camurati. 299-303
- Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based VerificationPrabhat Jain, Ganesh Gopalakrishnan. 304-307
- Reducing the Cost of Test Pattern Generation by Information ReusingWeidong Li, Carl McCrosky, Mostafa H. Abd-El-Barr. 310-313
- A Comparative Evaluation of Adders Based on Performance and TestabilityRathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.. 314-317
- A Memory Controller with an Integrated Graphics ProcessorJohn Watkins, Raymond Roth, Michael Hsieh, William Radke, Donald Hejna, Byung Kim, Richard Tom. 324-338
- Trail: A Track-Based Logging Disk Architecture for Zero-Overhead WritesTzi-cker Chiueh. 339-343
- Multiple-Page Translation for TLBLishing Liu. 344-349
- Optimal Scheduling of Finite-State MachinesTi-Yen Yen, Wayne Wolf. 366-369
- Global Mobility Based SchedulingUsha Prabhu, Barry M. Pangrle. 370-373
- Cluster-Oriented Scheduling in Pipelined Data Path SyntesisChing-Tang Chang, Kenneth Rose, Robert A. Walker. 374-378
- Design Guidelines and Testability AssessmentB. R. Wilkins, C. Shi. 388-391
- String Matching on IDP: A String Matching Algorithm for Vector Processors and Its ImplementationYusuke Mishina, Keiji Kojima. 394-401
- A Systolic Array for Approximate String MatchingRaghu Sastry, N. Ranganathan. 402-405
- A Systolic Architecture for High Speed Pipelined MemoriesAlex G. Dickinson, C. J. Nicol. 406-409
- Pica: An Ultra-Light Processor for High-Througput ApplicationsD. Scott Wills, W. Stephen Lacy, Huy Cat, Michael A. Hopper, Ashutosh Razdan, Sek M. Chai. 410-414
- Low-Power Driven Technology Mapping under Timing ConstraintsBill Lin, Hugo De Man. 421-427
- Heuristic Minimization of Synchronous RelationsVigyan Singhal, Yosinori Watanabe, Robert K. Brayton. 428-433
- Derivation of a DRAM Memory Interface by Sequential DecompositionKamlesh Rath, Bhaskar Bose, Steven D. Johnson. 438-441
- Physically Realizable Gate ModelsPaul R. Stephan, Robert K. Brayton. 442-445
- Formal Semantics of VHDL for Verification of Circuit DesignsXin Hua, Hantao Zhang. 446-449
- Fast Timing Analysis for Hardware-Software Co-SynthesisW. Ye, Rolf Ernst, Thomas Benner, Jörg Henkel. 452-457
- System Factorization in Codesign: A Case Study of the Use of Formal Techniques to Achieve Hardware-Software DecompositionBhaskar Bose, M. Esen Tuna, Steven D. Johnson. 458-461
- Strongly NP-Hard Discrete Gate Sizing ProblemsWing Ning Li. 468-471
- An Exact Rectilinear Steiner Tree AlgorithmJeffrey S. Salowe, David M. Warme. 472-475
- Neighbour State Transition Method for VLSI Optimization ProblemsDian Zhou, F. Tsui. 476-479
- The Splash 2 Processor and ApplicationsJeffrey M. Arnold, Duncan A. Buell, Dzung T. Hoang, Daniel V. Pryor, Nabeel Shirazi, Mark R. Thistle. 482-485
- Beyond Superscalar Using FPGAsChristian Iseli, Eduardo Sanchez. 486-490
- A Field Programmable Accelerator for Compiled-Code ApplicationsDavid M. Lewis, Marcus van Ierssel, Daniel H. Wong. 491-496
- High Performance Embedded System Optimization Using Algebraic and Generalized Retiming TechniquesMiodrag Potkonjak, Sujit Dey, Zia Iqbal, Alice C. Parker. 498-504
- Some Results on the Complexity of Boolean Functions for Table Look Up ArchitecturesRajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 505-512
- Efficient Symbolic Support ManipulationBill Lin. 513-516
- Desgin for Testability of Asynchronous Sequential CircuitsJayashree Saxena, Dhiraj K. Pradhan. 518-522
- Pseudoexhaustive BIST for Sequential CircuitsDimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia. 523-527
- Test Path Generation and Test Scheduling for Self-Testable DesignsAlex Orailoglu, Ian G. Harris. 528-531
- Computer-Aided Redesign of VLSI Circuits for Hot-Carrier ReliabilityPing-Chung Li, Ibrahim N. Hajj. 534-537
- A Logic-Level Model for alpha-Paricle Hits in CMOS CircuitsHungse Cha, Janak H. Patel. 538-542
- Complex Gate Performance Improvement by Jog Insertion into Transistor GatesRonald D. Hindmarsh. 543-546
- A Framework for Specifying and Designing PipelinesMark Aagaard, Miriam Leeser. 548-551
- System-Level Specification of Instruction SetsTodd A. Cook, Paul D. Franzon, Edwin A. Harcourt, Thomas K. Miller III. 552-557
- Newton: Performance Improvement Through Comparative AnalysisLyle D. Kipp, David J. Kuck. 558-561
- Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow GraphShang-E Tai, Debashis Bhattacharya. 564-567
- MIXER: Mixed-Signal Fault SimulatorNaveena Nagi, Abhijit Chatterjee, Jacob A. Abraham. 568-571
- Functional Fault Models and Gate Level Coverage for Sequential ArchitecturesGiacomo Buonanno, Franco Fummi, Donatella Sciuto. 572-575
- An Adaptive Technique for Dynamic Rollback in Concurrent Event-Driven Fault SimulationLaura Farinetti, Pier Luca Montessoro. 576-582
- Influence of Error Correlations on the Signature Analysis AliasingRégis Leveugle, X. Delord, Gabriele Saucier. 584-587
- Phi-Test: Perfect Hashed Index Test for Test Response ValidationRajiv Gupta. 588-591
- Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor SystemsSanthanam Srinivasan, Niraj K. Jha. 592-595
- Quiescent Current Monitoring to Improve the Reliability of Electronic Systems in Space Radiation EnvironmentsF. L. Vargas, Michael Nicolaidis, Bernard Courtois. 596-600
- Fast CRC CalculationRené J. Glaise, X. Jacquart. 602-605
- Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive FiltersAbhijit Chatterjee, Rabindra K. Roy. 606-609
- Subterranean: A 600 Mbit/Sec Cryptographic VLSI ChipLuc J. M. Claesen, Joan Daemen, Mark Genoe, G. Peeters. 610-613