Robert A. Walker - researchr alias

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Viewing Publication 1 - 38 from 38

2011

MTASC: A Multithreaded Associative SIMD ProcessorKevin Schaffer, Robert A. Walker. ipps 2011: 1776-1780 [doi]

2008

Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded SystemsKen W. Batcher, Robert A. Walker. date 2008: 260-263 [doi]

Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD ProcessorKevin Schaffer, Robert A. Walker. ppl, 18(4):491-509, 2008. [doi]

Using hardware multithreading to overcome broadcast/reduction latency in an associative SIMD processorKevin Schaffer, Robert A. Walker. ipps 2008: 1-7 [doi]

2007

A Prototype Multithreaded Associative SIMD ProcessorKevin Schaffer, Robert A. Walker. ipps 2007: 1-6 [doi]

Perfect Hash Families: Constructions and ExistenceRobert A. Walker, Charles J. Colbourn. jmc, 1(2):125-150, 2007. [doi]

2006

Interrupt Triggered Software Prefetching for Embedded CPU Instruction CacheKen W. Batcher, Robert A. Walker. rtas 2006: 91-102 [doi]

Roux-type constructions for covering arrays of strengths three and fourCharles J. Colbourn, Sosina Martirosyan, Tran van Trung, Robert A. Walker. dcc, 41(1):33-57, 2006. [doi]

2005

A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded ApplicationsHong Wang 0007, Robert A. Walker. pdcs 2005: 667-673

2004

A Scalable Associative Processor with Applications in Database and Image ProcessingHong Wang 0007, Lei Xie, Meiduo Wu, Robert A. Walker. ipps 2004: [doi]

Cluster miss prediction for instruction caches in embedded networking applicationsKenneth E. Batcher, Robert A. Walker. glvlsi 2004: 358-363 [doi]

Cluster miss prediction with prefetch on miss for embedded CPU instruction cachesKen W. Batcher, Robert A. Walker. cases 2004: 24-34 [doi]

2003

Implementing a Scalable ASC ProcessorHong Wang 0007, Robert A. Walker. ipps 2003: 267 [doi]

2002

Implementing Associative Search and Responder ResolutionMeiduo Wu, Robert A. Walker, Jerry L. Potter. ipps 2002: [doi]

2001

Implementing Associative Processing: Rethinking EarlierArchitectural DecisionsRobert A. Walker, Jerry L. Potter, Yanping Wang, Meiduo Wu. ipps 2001: 195

2000

Efficient optimal design space characterization methodologiesStephen A. Blythe, Robert A. Walker. todaes, 5(3):322-336, 2000. [doi]

1999

Efficiently Searching the Optimal Design SpaceStephen A. Blythe, Robert A. Walker. glvlsi 1999: 192 [doi]

Bounding Algorithms for Design Space ExplorationSamit Chaudhuri, Robert A. Walker. glvlsi 1999: 234-235 [doi]

A practical one-semester VLSI design course for computer science (and other) majorsRobert A. Walker. sigcse 1999: 237-241 [doi]

1997

A solution methodology for exact design space exploration in a three-dimensional design spaceSamit Chaudhuri, S. A. Blthye, Robert A. Walker. tvlsi, 5(1):69-81, 1997. [doi]

1996

Toward a Practical Methodology for Completely Characterizing the Optimal Design SpaceStephen A. Blythe, Robert A. Walker. isss 1996: 8-13 [doi]

Computing lower bounds on functional units before schedulingSamit Chaudhuri, Robert A. Walker. tvlsi, 4(2):273-279, 1996. [doi]

1995

An exact methodology for scheduling in a 3D design spaceSamit Chaudhuri, Stephen A. Blythe, Robert A. Walker. isss 1995: 78-83 [doi]

Introduction to the Scheduling ProblemRobert A. Walker, Samit Chaudhuri. dt, 12(2):60-69, 1995. [doi]

1994

Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problemSamit Chaudhuri, Robert A. Walker, J. E. Mitchell. tvlsi, 2(4):456-471, 1994. [doi]

ILP-Based Scheduling with Time and Resource Constraints in High Level SynthesisSamit Chaudhuri, Robert A. Walker. vlsid 1994: 17-20

Computing lower bounds on functional units before schedulingSamit Chaudhuri, Robert A. Walker. isss 1994: 36-41 [doi]

Guest Editor s Introduction: The Status of High-Level SynthesisRobert A. Walker. dt, 11(4):42-43, 1994.

1993

Cluster-Oriented Scheduling in Pipelined Data Path SyntesisChing-Tang Chang, Kenneth Rose, Robert A. Walker. iccd 1993: 374-378

The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling ProblemSamit Chaudhuri, Robert A. Walker, John Mitchell. iccd 1993: 25-29

1991

Increasing User Interaction During High-Level SynthesisRobert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland. micro 1991: 133-142 [doi]

1989

Behavioral transformation for algorithmic level IC designRobert A. Walker, Donald E. Thomas. tcad, 8(10):1115-1128, 1989. [doi]

1988

The System Architect s WorkbenchDonald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn. dac 1988: 337-343 [doi]

1985

MATRIXx/PC: Modeling, simulation, and optimization on personal computersRobert A. Pine, Robert A. Walker, Narendra K. Gupta. pieee, 73(12):1817-1825, 1985. [doi]

A model of design representation and synthesisRobert A. Walker, Donald E. Thomas. dac 1985: 453-459 [doi]

1983

Automatic Data Path SynthesisDonald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker. Computer, 16(12):59-70, 1983.

Behavioral level transformation in the CMU-DA systemRobert A. Walker, Donald E. Thomas. dac 1983: 788-789 [doi]

1982

Remark on Algorithm 506: HQR3 and EXCHNG: Fortran Subroutines for Calculating and Ordering the Eigenvalues of a Real Upper Hessenberg Matrix David S. Flamm, Robert A. Walker. TOMS, 8(2):219-220, 1982. [doi]

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