Abstract is missing.
- Hardware/software co-verification in ATMGiovanni Mancini. 1-7 [doi]
- A methodology for simulation and synthesis of mixed hardware/software systemsAsawaree Kalavade, Edward A. Lee. 10 [doi]
- Instruction set definition and instruction selection for ASIPsJohan Van Praet, Gert Goossens, Dirk Lanneer, Hugo De Man. 11-16 [doi]
- Data routing: a paradigm for efficient data-path synthesis and code generationDirk Lanneer, Marco Cornero, Gert Goossens, Hugo De Man. 17-22 [doi]
- Timing analysis for synthesis in microprocessor interface designMarco A. Escalante, Nikitas J. Dimopoulos. 23-28 [doi]
- Applications of attributed-behavior synthesisLawrence F. Arnstein, Donald E. Thomas. 29-34 [doi]
- Computing lower bounds on functional units before schedulingSamit Chaudhuri, Robert A. Walker. 36-41 [doi]
- Timing estimation for behavioral descriptionsDoron Mintz, Carlos Dangelo. 42-47 [doi]
- Efficient timing constraint derivation for optimal retiming high speed processing unitsAlbert van der Werf, Jef L. van Meerbergen, Emile H. L. Aarts, Wim F. J. Verhaegh, Paul E. R. Lippens. 48-53 [doi]
- SMASH: a program for scheduling memory-intensive application-specific hardwarePravil Gupta, Alice C. Parker. 54-59 [doi]
- Ensemble representation and techniques for exact control-dependent schedulingIvan P. Radivojevic, Forrest Brewer. 60-65 [doi]
- Is high-level synthesis marketable? (panel)Leon Stok. 66 [doi]
- State-of-the-art compiler optimizationF. Kenneth Zadeck. 67-68 [doi]
- An integrated approach to retargetable code generationThomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji. 70-75 [doi]
- Bit-alignment for retargetable code generatorsKoen Schoofs, Gert Goossens, Hugo De Man. 76-81 [doi]
- Code generation for a DSP processorWei-Kai Cheng, Youn-Long Lin. 82-87 [doi]
- Retargetable assembly code generation by bootstrappingRainer Leupers, Wolfgang Schenk, Peter Marwedel. 88-93 [doi]
- CodeSyn: a retargetable code synthesis system (abstract)Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala. 94 [doi]
- Concurrent testing in high-level synthesisRavibala Singh, John Knight. 96-103 [doi]
- Testing two-phase transition signaling based self-timed circuits in a synthesis environmentPrabhakar Kudva, Venkatesh Akella. 104-111 [doi]
- A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designsChih-Tung Chen, Alice C. Parker. 112-117 [doi]
- A divide-and-conquer approach for asynchronous interface synthesisRuchir Puri, Jun Gu. 118-125 [doi]
- Rapid prototyping of fault-tolerant VLSI systemsRamesh Karri, Karin Högstedt, Alex Orailoglu. 126-131 [doi]
- ASICs vs ASIPs (panel)Peter Marwedel. 132 [doi]
- Specification of interface components for synchronous data pathsPeter Gutberlet, Wolfgang Rosenstiel. 134-139 [doi]
- Global node reduction of linear systems using ratio analysisMichael Sheliga, Edwin Hsing-Mean Sha. 140-145 [doi]
- A specification invariant technique for operation cost minimisation in flow-graphsMartin Janssen, Francky Catthoor, Hugo De Man. 146-151 [doi]
- Controller and datapath trade-offs in hierarchical RT-level synthesisD. Sreenivasa Rao, Fadi J. Kurdahi. 152-157 [doi]
- How datapath allocation affects controller delaySteve C.-Y. Huang, Wayne Wolf. 158-163 [doi]
- An algorithm for the allocation of functional units from realistic RT component librariesRoger P. Ang, Nikil Dutt. 164-169 [doi]